Track: By me composed! Xe-xe.. :)
Author: Macros, 14 July 2K1.
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Dynamic memory chips.
------------------------------
Pin layout for single-bit mics
DRAM chips (*A10 for 1M*1 chips is not
used)
DIP-16 SOJ-26/20
256K*1 1M*1;4M*1
+-+---+ +-+----+
A8+1 16+Vss Din+1 26+Vss
Din+ +CAS# WE#+------+Dout
WE#+ +Dout RAS#+ +CAS#
RAS#+ +A6 NC+ +NC
A0+ +A3 *A10+5 22+A9
A2+ +A4 | |
A1+ +A5 | |
Vcc+8 9+A7 A0+9 18+A8
+-----+ A1+ +A7
A2+ +A6
A3+ +A5
Vcc+13 14+A4
+------+
DIP-18 ZIP-20
1M*11M*1
4M*1 4M*1
+-+----+ /
Din+1 18+Vss A9 1|-|_|2 CAS#
WE#+ +Dout Dout 3|-|_|4 Vss
RAS#+ +CAS# Din 5|-|_|6 WE#
*A10+ +A9 RAS# 6|-|_|8 *A10
A0+ +A8 NC 9|-|_|10 NC
A1+ +A7 A0 11|-|_|12 A1
A2+ +A6 A2 13|-|_|14 A3
A3+ +A5 Vcc 15|-|_|16 A4
Vcc+9 10+A4 A5 17|-|_|18 A6
+------+ A7 19|-|_|20 A8
/
Pinout location of four-bit mics
DRAM circuits (*A9 for 256K chips*4 not
used)
DIP-18 SOJ26/20
64K*1 256K*4
1M*4
+-+---+ +-+---+
OE#+1 18+Vss DQ1+1 26+Vss
DQ1+ +DQЧ DQ2+-----+DQЧ
DQ2+ +CAS# WE#+ +DQЗ
WE#+ +DQЗ RAS#+ +CAS#
RAS#+ +A0 *A9+5 22+OE#
A6+ +A1 | |
A5+ +A2 | |
A4+ +A3 A0+9 18+A8
Vcc+9 10+A7 A1+ +A7
+-----+ A2+ +A6
A3+ +A5
Vcc+13 14+A4+-----+
DIP-20
256K*4 ZIP20
1M*4 256k*4
1M*4
+-+---+
DQ1+1 20+Vss /
DQ2| +DQЧ OE# 1|-|_|2 CAS#
WE#+ +DQЗ DQЗ 3|-|_|4 DQЧ
RAS#+ +CAS# Vss 5|-|_|6 DQ1
*A9+ +OE# DQ2 7|-|_|8 WE#
A0+ +A8 RAS# 9|-|_|10 *A9
A1+ +A7 A0 11|-|_|12 A1
A2+ +A6 A2 13|-|_|14 A3
A3+ +A5 Vcc 15|-|_|16 A4
Vcc+10 11+A4 A5 17|-|_|18 A6
+-----+ A7 19|-|_|20 A8
/
Расположение выводов двухбайтных мик-
росхем DRAM
SOJ-4OOmil
256K*16
256K*18
+-+-----+
Vcc+1 40+Vss
DQ1+ +DQ16
DQ2+ +DQ15
DQЗ+ +DQ14
DQЧ+ +DQ13
Vcc+ +Vss
DQS+ +DQ12
DQб+ +DQ11DQ7+ +DQ10
DQ8+ +DQ9
DQO+ +P11
NC+ +CASL#
WE#+ +CASH#
RAS#+ +OE#
NC+ +A8
A0+ +A7
A1+ +A6
A2+ +A5
A3+ +A4
Vcc+20 21+Vss
+-------+
+=======+===============+
|Signal | Destination |
+=======+===============+
|RAS# | Row Access Strobe |
| | Row address sampling strobe. |
| | As the signal declines |
| | any circulation cycle, low |
| | level is maintained for everything |
| | cycle time. |
+-------+------------------------------+
|CAS# | Column Access Strobe |
| | Column address sampling strobe.|
| | As the decline begins, the cycle begins |
| | writing or reading. |
+-------+------------------------------+
|MAi | Multiplexed Address |
| | Multiplexed lines |
| | addresses. During the recession, sig- |
| | RAS# on these lines at-|
| | address availablelines, in |
| | fall time CAS# - address |
| | column. |
+-------+------------------------------+
|WE# | Write Enable |
| | Recording permission. Data for- |
| | are written to the selected cell|
| | by CAS# decline at low |
| | level WE# (Early entry, |
| | normal option), or by |
| | decline in WE# at a low level |
| | CAS# (Delayed Recording). |
| | WE# goes low |
| | and back with high CAS# |
| | does not cause entries, but only |
| | translates EDO output buffer |
| | DRAM in high impedance |
| | state. |
+-------+------------------------------+
|OE# | Output Enable |
| | Permission to open the weekend|
| | buffer during a read operation. |
| | High signal level in lu-|
| | fight moment transfers day off|
| | buffer in high impedance |
| | state. |
+-------+------------------------------+
|DB-In | Data Bit Input |
| | Input data (only for |
| | microcircuits with one-bit organi- |
| | nization) |
+-------+------------------------------+
|DB-Out | Data Bit Output|
| | Output data (only for |
| | microcircuits with one-bit organi- |
| | nization). Output Buffers |
| | standard chips are open|
| | only with a combination of low |
| | signal level RAS#, CAS#, |
| | OE# and high level WE#; |
| | if any of the |
| | these conditions the buders pass |
| | into a high-impedance state- |
| | tion. EDO chips have weekends|
| | buffers are open even after lifting |
| | ma signal CAS#. |
+-------+------------------------------+
|DQx | Data Bit |
| | United inside micro |
| | circuits input and output sig- |
| | data files. |
+-------+------------------------------+
|NC | No connection |
| | Free withdrawal. |
+=======+===============+
Static memory chips
DIP-28
8K*8 (pin 1.26 not used)
16K*8 (pin 1 not used)
+-+----+ DIP-32
*A14+1 28+Vcc 64K*8 (pin 2 not used)
A12+ +WE# 128K*6
A7+ +A13*
A6+ +A8 +-+----+A5+ +A9 NC+1 32+Vcc
A4+ +A11 *A16+ +A15*
A3+ +OE# A14+ +CE2*
A2+ +A10 A12+ +WE#
A1+ +CE# A7+ +A13
A0+ +DQ7 A6+ +A8
DQO+ +DQб A5+ +A9
DQ1+ +DQS A4+ +A11
DQ2+ +DQЧ A3+ +OE#
GND+14 15+DQЗ A2+ +A10
+------+ A1+ +CE1#
A0+ +DQ7
DQO+ +DQб
DQ1+ +DQS
DQ2+ +DQC
GND+16 17+DQЗ
+------+
Mobile phone SIMM-30
+-----------------------------+
| +-----+ +-----+ +-----+ |
| | | | | | | |
| | | | | | | |
|o +-----+ +-----+ +-----+ o|
++ |
| 1 ||||||||||||||||||||| 30 |
+----------------------------+
Pin assignment of SIP and SIMM modules
STD - Standard SIMM (SIPP)
IBM is a SIMM company
+-------+------------+------------+
|Contact| STD | IBM |
+-------+------------+------------+
| 1 | +5V | +5V |
| 2 | CAS# | CAS# |
| 3 | DQO | DQO |
| 4 | MAO | MAO |
| 5 | MA1| MA1|
| 6 | DQ1| DQ1|
| 7 | MA2 | MA2 |
| 8 | MAZ | MAZ |
| 9 | GND| GND|
| 10 | DQ2 | DQ2 |
| 11 | MATCH | MATCH |
| 12 | MAS | MAS |
| 13 | DQZ | DQZ |
| 14 | MAb | MAb |
| 15 | MA7 | MA7 |
| 16 | DQCH | DQCH |
| 17 | MA8| MA8|
| 18 | MA9 | MA9 |
| 19 | MA10 | RAS1# |
| 20 | DQS | DQS |
| 21 | WE#| WE#|
| 22 | GND| GND|
| 23 | DQb | DQb |
| 24 | NC | PD (GND) |
|25 | DQ7 | DQ7 |
| 26 | PB-Out | PD(1M-GND)|
| 27 | RAS# RASO# | |
| 28 | CAS-Parity#| NC |
| 29 | PB-In | PB-(In/Out)|
| 30 | +5V | +5V |
+-------+-----------+------------+
Signals of SIMM modules
+===========+-----------------------+
|MAi | Multiplexed Address |
+------------+-----------------------+
|DQx | Data Bit (merged |
| |exits and entrances. |
+------------+-----------------------+
|PQx | Parity Bit - bit |
| |parity of the x-th byte. |
+-----------+-----------------------+
|PB-In | Parity Bit Input |
+------------+-----------------------+
|PB-Out | Output - input and output |
| | microcircuits bit pari- |
| |theta. For storage pa- |
| | Rite in these modules |
| |always used |
| |chips with one-bit|
| |organizations that|
| |input and output are separated. |
| |Usually these contacts are on |
| |module connected. |
+------------+-----------------------+
|WE# | Write Enable |+------------+-----------------------+
|RASx# |Row selection strobes. |
| |RAS#0 and RAS#1 use-|
| |are accordingly for|
| | bits 0-15 and 16-31. |
+------------+-----------------------+
|CASx# |Sampling gates column- |
| |tsov, separate for each |
| | a lot of bytes. |
+-----------+-----------------------+
|CAS-Parity# |Column sampling strobe |
| |for control times- |
| | rows. |
+------------+-----------------------+
|OEx# | Output Enable |
+------------+-----------------------+
|PD1-5 | Presence Detect |
| |Presence indicators |
| |(usually not used) |
+------------+-----------------------+
|NC | No connection |
| |Free withdrawal |
+===========+-----------------------+
Resisting memory
DIP-24 DIP-28
+-+---+ +-+---+
A7+1 24+Vcc Vpp/*A15+1 28+Vcc
A6+ +A8 A12+ +PGM#/A14*
A5+ +A9 A7+ +A13
A4+ +A11/Vpp* A6+ +A8
A3+ +OE#/Vpp* A5+ +A9A2+ +A10 A4+ +A11
A1+ +CE# A3+ +OE#/Vpp*
A0+ +DQ7 A2+ +A10
DQO+ +DQб A1+ +CE#
DQ1+ +DQS A0+ +DQ7
DQ2+ +DQЧ DQO+ +DQб
GND+12 13+DQЗ DQ1+ +DQS
+-----+ DQ2+ +DQЧ
GND+14 15+DQЗ
+-----+
TSOP-32 DIP-32
+-+------+ +-+---+
Vpp+1 32+OE# Vpp+1 32+Vcc
A16+ +A10 A16+ +PGM#
A15+ +CE# A15+ +A17*
A12+ +DQ7 A12+ +A14
A7+ +DQб A7+ +A13
A6+ +DQS A6+ +A8
A5+ +DQЧ A5+ +A9
A4+ +DQЗ A4+ +A11
A3+ +GND A3+ +OE#
A2+ +DQ2 A2+ +A10
A1+ +DQ1 A1+ +CE#
A0+ +DQO A0+ +DQ7
DQO+ +A0 DQO+ +DQб
DQ1+ +A1 DQ1+ +DQS
DQ2+ +A2 DQ2+ +DQЧ
GND+16 17+A3 GND+16 17+DQЗ
+--------+ +-----+
+==============+========+===============+
|Микросхема и | Корпус| Примечание |
|организация | | |+==============+=======+===============+
|2716 - 2K*8 |DIP-24 |20=OE#; 21=Vpp |
|2732 - 4K*8 |DIP-24 |20=OE#/Vpp |
| | |21=A11 |
|2764 - 8K*8 |DIP-28 |1=Vpp; 22=OE# |
| | |26=NC; 27=PGM# |
|27128 - 16K*8 |DIP-28 |1=Vpp; 22=OE# |
| | |26=A13; 27=PGM#|
|27256 - 32K*8 |DIP-28 |1=Vpp; 22=OE# |
| | |26=A13; 27=A14 |
|27512 - 64K*8 |DIP-28 |1=Vpp; |
| | |22=OE#/Vpp |
| | |26=A13; 27=A14 |
|27010 - 128K*8|DIP-32 |30=NC |
|27010 - 128K*8|TSOP-32|6=NC |
|27010 - 128K*8|PLCC-32|30=NC |
|27020 - 256K*8|DIP-32 |- |
|27020 - 256K*8|TSOP-32|- |
|27020 - 256K*8|PLCCЗ2 |- |
+--------------+-------+---------------+
+====+---------------------------------+
|CE# |Выборка микросхемы. |
+----+---------------------------------+
|OE# |Разрешение чтения данных из м/сх.|
| | |
|DQx |Двунаправленные линии шины данных|
+----+---------------------------------+
|Ax |Входные линии шины адреса. Линия |
| |A9 допускает подачу высокого |
| |(12 В) напряжения для чтения кода|
| |производителя (A0=0) и устройства|
| |(A0=1), при этом на остальные |
| |адресные линииlog is submitted."0" |
+----+---------------------------------+
|PGM#|Programming pulse. |
| |Some chips do not have |
| | this signal, their programming |
| |signal is carried out by signal CE#|
| |at a high Vpp level. |
+-------------------+---------------------------------+
|Vpp |Programming voltage pi- |
| | tania. For some types - |
| |impulse |
+-------------------+---------------------------------+
|Vcc |Power (+5 V) |
+====+---------------------------------+
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