Track: By me composed! Xe-xe.. :)
Author: Macros, 14 July 2K1.
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Разъемы шин ISA 8/16 бит, EISA
+======+========+====+=======+=========+
|Ряд F |Ряд B | N# |Ряд A |Ряд E |
+------+--------+----+-------+---------+
|GND |GND | 1 |IOCHK |CMD# |
+------+--------+----+-------+---------+
|+5 В |Reset | 2 |Data 7 |START# |
+------+--------+----+-------+---------+
|+5 В |+5 В | 3 |Data 6 |EXRDY |
+------+--------+----+-------+---------+
|Unused|IRQ2/9*1| 4 |Data 5 |EXЗ2# |
+------+--------+----+-------+---------+
|Unused|-5 В | 5 |Data 4 |GND |
+------+--------+----+-------+---------+
|Key |DRQ2 | 6 |Data 3 |Key |
+------+--------+----+-------+---------+
|Unused|-12 В | 7 |Data 2 |EX16# |
+------+--------+----+-------+---------+
|Unused|OWS#*2 | 8 |Data 1 |SLBURST# |
+------+--------+----+-------+---------+
|+12 В |+12 В | 9 |Data 0 |MSBURST# |
+------+--------+----+-------+---------+
|M/-IO |GND | 10 |IOCHDRY|W/R# |+------+--------+----+-------+---------+
|-LOCK |SmemWR# | 11 |AENx |GND |
+------+--------+----+-------+---------+
|Reserve|SmemRD# | 12 |Addr 19|EMBbb#*3 |
+------+--------+----+-------+---------+
|GND |IO WR# | 13 | 18|EMB133#*3|
+------+--------+----+-------+---------+
|Reserve|IO RD# | 14 | 17|Reserve |
+------+--------+----+-------+---------+
|BE 3# |DACKZ# | 15 | 16|GND |
+------+--------+----+-------+---------+
|Key |DRQZ | 16 | 15|Key |
+------+--------+----+-------+---------+
|BE 2# |DACK1# | 17 | 14|BE 1# |
+------+--------+----+-------+---------+
|BE 0# |DRQ 1 | 18 | 13|LA 31# |
+------+--------+----+-------+---------+
|GND |Ref# | 19 | 12|GND |
+------+--------+----+-------+---------+
|+5 V |Bclock | 20 | 11|LA 30# |
+------+--------+----+-------+--------+
|LA 29#|IRQ7 | 21 | 10|LA 28# |
+------+--------+----+-------+---------+
|GND |IRQb | 22 | 9 |LA 27# |
+------+--------+----+-------+---------+
|LA 26#|IRQS | 23 | 8 |LA 25# |
+------+--------+----+-------+---------+
|LA 24#|IRQC | 24 | 7 |GND |
+------+--------+----+-------+---------+
|Key |IRQZ | 25 | 6 |Key |
+------+--------+----+-------+---------+
|LA 16 |DACK 2# | 26 | 5 |LA 15 |+------+--------+----+-------+---------+
|LA 14 |TC | 27 | 4 |LA 13 |
+------+--------+----+-------+---------+
|+5 V |BALE | 28 | 3 |LA 12 |
+------+--------+----+-------+---------+
|+5 V |+5 V | 29 | 2 |LA 11 |
+------+--------+----+-------+---------+
|GND |Osc | 30 | 1 |GND |
+------+--------+----+-------+---------+
|LA 10 |GND | 31 |Addr 0 |LA 9 |
+------+--------+====+-------+---------+
*1 - B4: XT=IRQ2, AT=IRQ9
*2 - B8: XT=Card Selected
*3 - E12,E13 - for Fast EISA only
ISA slot
D18 D1 B31 B1
+============+ +======================+
|+----------+| |+---------------------+|
|+----------+| |+---------------------+|
+============+ +======================+
C18 C1 A31 A1
EISA bus connector
| | | | | |
+++ +++ +++ +++ +++ +++ Contacts ISA
| ||| ||| | | ||| ||| | <------------
+-+|+-+|+-+ +-+|+-+|+-+ rows A,B,C,D
+++ +++ +=+ +++ +++
| | | | | | | | | | Contacts EISA
+-+ +-+ | | +-+ +-+ <-------------
===========++=========== rows E,F,G,H
EISA Key
Optional 1bbt ISA bus connectors,
EISA:
+=======+=======+====+=======+======+
| Row H | Row D | N# | Row C | Row G |
+-------+-------+----+-------+-------+
|LA 8 |MCS16# | 1 |SBHE# |LA 7 |
+-------+-------+----+-------+-------+
|LA 6 |IOCS16#| 2 |LA 23 |GND |
+-------+-------+----+-------+-------+
|LA 5 |IRQ 10 | 3 |THE 22 |THE 4 |
+-------+-------+----+-------+-------+
|+5 V |IRQ 11 | 4 |THE 21 |THE 3 |
+-------+-------+----+-------+-------+
|LA 2 |IRQ 12 | 5 |LA 20 |GND |
+-------+-------+----+-------+-------+
|Key |IRQ 15 | 6 |LA 19 |Key |
+-------+-------+----+-------+-------+
|Data 16|IRQ 14 | 7 |LA 18 |Date 17|
+-------+-------+----+-------+-------+
|Data 18|DACKO# | 8 |LA 17 |Date 19|
+-------+-------+----+-------+-------+
|GND |DRQ 0 | 9 |MemRD# |Data 20|
+-------+-------+----+-------+-------+
|Data 21|DACKS# | 10 |MemWR# |Data 22|
+-------+-------+----+-------+-------+
|Data 23|DRQ 5 | 11 |Data 8 |GND |
+-------+-------+----+-------+-------+
|Data 24|DACKb# | 12 |Date 9 |Date 25|+-------+-------+----+-------+-------+
|GND |DRQ 6 | 13 | 10|Data 26|
+-------+-------+----+-------+-------+
|Data 27|DACK7# | 14 | 11|Data 28|
+-------+-------+----+-------+-------+
|Key |DRQ7 | 15 | 12|Key |
+-------+-------+----+-------+-------+
|Data 29|+5 V | 16 | 13|GND |
+-------+-------+----+-------+-------+
|+5 V |Master | 17 | 14|Data 30|
+-------+-------+----+-------+-------+
|+5 V |GND | 18 |Data 15|Data 31|
+-------+-------+----+-------+-------+
|MAKx# |- | 19 |- |MREQx |
+-------+-------+====+-------+-------+
Directly to the software address
entry to memory cells and space input
yes/output include the following signals:
DataO-Data 7 - data bus
AdrO-Adr19 - address bus
AEN - port addressing resolution (recorded
-resolves false decryption in DMA mode)
IOWR# - write to port
IORD# - read from port
SMemWR# - write to memory
SMemRD# - reading from memory
To interrupt and channel request signals
Direct memory access lams include
the following:
IRQ2/0, IRQЗ-IRQ7 - Interrupt requests.
A positive signal difference causes
hardware interrupt request. For iden-
source identificationhigh level of debt
wife will be saved until the interruption is confirmed
processor, which makes it difficult to separate
Designated use of request lines. Lee-
IRQ2/9 on XT buses causes hardware
interruption with number 2, and in AT - with
number 9.
DRQ1-DRWЗ - requests for 8-bit channels
DMA (positive edge).
DACK1#-DACKЗ# - confirmation of requests
8-bit DMA channels.
TC - cycle counter completion sign
DMA.
The bus also has several service signals
catch synchronization, reset, regeneration
memory installed on adapters:
IOCHRDY - device readiness, low
cycle lengthens the current cycle (no more than 15
mks).
BALE - address latch enable. After
its decline in each processor cycle is
AdrO-19 research institutes are guaranteed to contain
valid address.
Refr# - memory regeneration cycle (in XT
it's called DACKO#). The signal appears
every 15 µs, while the address bus indicates
calls for the next regenerated building
ku memory.
IOCHK - channel control, low level
calls the NMI CPU (enable and display
in system ports 061h, 062h)
Reset - hardware reset signal (acc.
tive level -high).
BClock - bus synchronization with frequency
about 8 MHz. Peripherals can be
Gut and do not use this signal, it works
recording only by control signals
si and reading.
OSC - not synchronized with the bus hour -
tota 14.431818 MHz (used st-
other display adapters).
Additional bus expansion connector
up to 16-bit, contains additional
address lines, interrupt requests and ca-
direct access cash:
Data 8-15 - data bus
SBHE - a sign of the presence of data on the lines
-Data 15-18
LA17-23 - non-fixed address signals
sa, requiring latching on the decline of the sig-
nala BALE. This method of submitting an address
reduces latency and circuits
memory address decoder for expansion boards
niya start decoding several
before the BALE decline.
IRQ10-12, IRQ 14-15 - additional
interrupt requests
DRQS-7 - 16-bit DMA channel requests
(positive difference)
DACKS-7# - confirmation of requests
16-bit DMA channels
With switching data bit depth
connected signals:
MCS16# - addressable device supporting
lives 16-bit memory accessesIOCS16# - addressable device supporting
lives 16-bit port access
New control signals include
the following:
MemWR# - write to memory
MemRD# - reading from memory
OWS# - signal from the device, allowing
On the system board, shorten the current cycle
(eliminate wait cycles)
MASTER# - request from the device used
using a 16-bit DMA channel on the package
tire management. Upon receipt
confirmation DACKS-7 Bus-Master can
seize the bus (no more than 15 µs)
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