Track: By me composed! Xe-xe.. :)
Author: Macros, 14 July 2K1.
-----------------------------------------
31+ +5v
+----+-+-+----+ Контроллер DMA
11+ CS |DMA|DAK1+25
|___ | |____|
3+MRD | |DAK2+24 8237A
|___ | |____|
4+MWR | |DAKЗ+14
|___ | |____|
1+IOR | |DAKЧ+15
|___ | +----+
2+IOW | | D0 +30
13+RES | | D1 +29
|___ | | D2 +28
36+EOP | | D3 +27
+----+ | D4 +26
19+DRQ1| | D5 +23
18+DRQ2| | D6 +22
17+DRQЗ| | D7 +21
16+DRQЧ| +----+
+----+ | A7 +40
6+RDY | | A6 +39
7+HLDA| | A5 +3812+CLK | | A4 +37
+----+ +----+
35+ A3 | |ASTB+8
34+ A2 | | AEN+9
33+ A1 | |HOLD+10
32+ A0 | | |
+----+-+-+----+
+20
Controller registers, R/W and their purpose
+===+-+--------------------------------+
|008|W| Command Register - configurator|
| |Bit 7 - 1=DACK active level |
| | high |
| |Bit 6 - 1=DRQ active level |
| | high |
| |Bit 5 - 1=extended recording mode|
| |Bit 4 - 1=cyclic priority |
| |Bit 3 - 1=shortened exchange cycle |
| |Bit 2 - 1=prohibition of the controller-|
| | ra |
| |Bit 1 - 1=fix channel address 0|
| |Bit 0 - 1=memory-to-memory transfer |
+---+-+--------------------------------+
|008|R| Status Register - status of ka-|
| |cash |
| |Bits 4-7 - requests for channels 0-3 |
| |Bits 0-3 - end of the channel cycle- |
| | catch 0-3 |
+---+-+--------------------------------+
|009|W| Request Register - register for- |
| |requests |
||Bits 7-3 - not used |
| |Bit 2 - 1=set/0=reset bit |
| | masks |
| |Bits 1-0 - channel selection |
| | 00=0 |
| | 01=1 |
| | 10=2 |
| | 11=3 |
+---+-+--------------------------------+
|00A|W| Single Mask Bit Register -masks|
| |Bits 7-3 - not used |
| |Bit 2 - 1=set/0=reset bit |
| | masks |
| |Bits 1-0 - channel selection |
+---+-+--------------------------------+
|00B|W| Mode Register - operating mode |
| |channels |
| |Bits 7-6 - transmission mode: |
| |00=on request |
| |01=single |
| |10=block |
| |11=cascading |
| |Bit 5 - 1=increment/0=decrement |
| | addresses |
| |Bit 4 - 1=auto-init enable-|
| | tions |
| |Bits 3-2 - transmission type |
| |00=idle |
| |01=record |
| |10=reading |
| |Bits 1-0 - channel selection |
+---+-+--------------------------------+
|00C|W| Clear Byte PointerFlip/Flop - |
| |Reset low byte trigger |
+---+-+--------------------------------+
|00D|W| Master Clear - general reset 8237|
| |(output any byte into the register you- |
| |calls reset) |
+---+-+--------------------------------+
|00E|W| Clear Mask Regiter - general reset|
| |masks of all channels (output of any |
| | byte into the register causes a reset) |
+---+-+--------------------------------+
|00F|W| All Mask Register Bits
| |masks of all channels |
| |Bits 0-3 - channel masks 0-3 |
| |0=channel enabled |
| |1=channel masked |
| |Bits 4-7 are not used |
+===+------------------------------------------------+
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