Track: By me composed! Xe-xe.. :)
Author: Macros, 14 July 2K1.
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+--------+
11+D0 IRO+18
10+D1 IR1+19 Контроллер прерываний
9+D2 IR2+20
8+D3 IRЗ+21 i8259A
7+D4 IRЧ+22
6+D5 IRS+23
5+D6 IRб+24
4+D7 IR7+25
27+A0 |
1+CS# |
3+RD# |
2+WR# |
17+INT |
26+INTA |
+--------+
Маскируемые прерывания обслуживаются
контроллером 8259A. Этот контроллер име-
ет 8 входов запросов прерываний IRQx от
внешних источников и выход запроса INTR,
по которому запрос поступает на однои-
менный вход процессора. При обработке
запроса INTRthe processor forms the bus
INTA interrupt acknowledge cycle, in
in which the controller transmits data via the bus
8-bit interrupt vector. This one
the vector is the number by which
reference to interrupt routine
stored in the interrupt table.
Initialization commands are designated
ICW1-ICWЧ and are sent by instructions
8-bit output to controller ports.
The first byte of ICW1 is sent to the address
020h, bytes ICW2-ICWЧ are sent via ad-
Resu 021h (in PC).
Byte ICW1 - controller configurator.
- Bits 7-5=0 (not used in PC)
- Bit 4=1 - sign of the initialization command -
+tions (in control commands from zero)
- Bit 3 - sensitivity of request lines
sa:
0=edge interrupt
1=level interrupt
- Bit 2=0 (not used in PC)
- Bit 1 - switching circuit
1=single controller (XT)
0=cascade activation (AT)
- Bit 0 - sign of using ICWЧ
Byte ICW2 specifies the starting vector number
ditch generated by this controller, in
interrupt table. Bits 2-0 must have
zero values.
The ICWЗ byte is used only for
cadence inclusion.
For the master controller, bytes 0-7uka-
call for the presence of slave controllers on
lines IRQO-IRQ7 respectively.
For the slave controller, bits 0-2 co-
keep the IRQ number of the master controller, to
to which it is connected, bits 3-7=0
The ICWЧ byte specifies the operating mode of the control
ler, its use is mandatory when
initial initialization (in XT - third byte
initialization)
- Bits 5-7 are not used
- Bit 4 - SFNM - enables nested mode
differences in the priorities of the leader's requests and
slave controllers
- Bit 3 - BUF - buffered sign
Stu tires.
- Bit 2 - M/S - position in the cascade:
1=master, 0=slave
- Bit 1 - AEOI - automatic resolution
ical completion of the interrupt (which is not
requires the mask bit to be reset upon completion
request service)
- Bit 0 - type of processor used:
N 1=8086/8088 and older, 0=8080
In operating mode the controller
accepts control commands
OCW1-OCWЗ. OCW1 is sent to the address
021h, OCW2, OCWЗ - at address 020h (in PC).
Byte OCW1 - request masks, single
bit value means recording masking
dew
- Bits 0-7 8259#1 - request masks
IRQO-IRQ7- Bits 0-7 8259#2 - request masks
IRQ8-IRQ15
Byte OSW2 - completion of service
(EOI), priority control.
- Bits 7-5 set the opcode:
001 - nonspecific EOI (AEOI=1 in
ICWЧ)
011* - specific EOI for the request
LLL
101 - nonspecific EOI with rotation
priority
100 - setting the priority rotation mode
theta
000 - reset priority rotation mode
111* - specific EOI with rotation
priority
110* - setting the lowest priority
010 - no operation In operations,
marked with an asterisk are used
bits 2-0 (LLL field)
- Bits 4-3=00 - OCW2 sign
- Bits 2-0 - LLL field - level number, k
to which the command applies.
Byte OCWЗ - operational control
controller
- Bit 7=0
- Bits 6-5 special masking mode
Vania (not used on PC):
11 - install
10 - reset
00.01 - do not change
- Bits 4-3=01 - OCWЗ sign
- Bit 2=0 -prohibits polishing mode (in
in which the interrupt request to the processor is not
is being produced)
- Bits 1-0 - control of reading re-
histrov:
10=read IR - mask register
11=reading IS - service register
my interruption
00.01 - do not change case
To read mask register or register
serviced interrupt (depending on
from bits 1-0 OCWЗ) port 021h is used
(in PC).
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