Hardware - Serial interfaces.

Track: By me composed! Xe-xe.. :)  
Author: Macros, 14 July 2K1.             
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      Serial interfaces        
      -----------------------        

 COM port                                
 --------                                

  When transmitting asynchronously, each byte
preceded by a start bit signaling
to the receiver about the beginning of the next sending, for
followed by data bits, and possibly
but, parity bit (parity check).
The transmission ends with a stop bit, I guarantee
giving a certain shutter speed between adjacent
parcels (see picture below). Start bit
the next byte sent can be sent
get started at any time after finishing
stop bit, that is, between gears
Pauses of arbitrary duration are possible.
The start bit, which always has a strictly defined
divided value (log. 0), provides
simple receiver synchronization mechanism
according to the transmitter signal.It is implied
that the receiver and transmitter are working on
one exchange rate, measured in co-
number of transmitted bits per second.
Internal clock generator
the receiver uses a counter-divider
reference frequency, reset at the moment
receiving the start of the start bit.  This counter
generates internal strobes, according to which
the receiver records the last received
bits.                                    

 Asynchronous transmission format:            

          Start Stop       
           bit bit       
     |     +-+-+-+-+-+-+-+-+-+-+ +------ 
Log.0|Pause| | | | | | | | | | | |next  
0 -+-----+-+-+-+-+-+-+-+-+-+-+-+------ 
Log. |     | |0|1|2|3|4|5|6|7|p| |before. 
     +-----+ +-+-+-+-+-+-+-+-+-+-+------ 
  Domestic                             
    strobes                               
 ------+-+-+-+-+-+-+-+-+-+--------- 

  The asynchronous sending format allows
identify possible transmission errors:       

  - If an edge is received signaling
about the beginning of the sending, and according to the start bit strobe
the level of logical unit is fixed,
the start bit is considered false and the receiver
goes back to the waiting state. About
this format error, the receiver may not
report.                                

  - If during the time allottedunder
stop bit(s), logic level detected
which unit, a stop bi- error is recorded
that (also a format error).                

  - If parity is used
(parity), then after sending the data bit
(before the stop bit) a control bit is transmitted
bit.  This bit complements the number
single data bits to even or
odd depending on the accepted
agreements.  Receiving a byte with an incorrect value
checking the check bit when the
parity control leads to fixation
received data errors.                  

  Synchronous transmission mode assumes
constant activity of the communication channel. By-
The link starts with a sync byte, for which
Crimea is closely followed by a flow of information
ny bits.  If the transmitter has no data
for transmission, it fills the pause
bursty sending of synchronization bytes.
External synchronization is possible either with
using a separate line for transmission
synchronization signal, or using
self-timed coding
data, in which on the receiving side
from the received signal can be extracted
and synchronization pulses.                

 RS-232C interface                       
 -----------------                       

  The RS-232C standard uses unbalancedrich transmitters and receivers - signal
transmitted relative to the common wire -
schematic land. The interface does not provide
galvanic isolation of devices. Logi-
the logical unit corresponds to the level
voltage at the receiver input in the range
zone -12...-3 V. For control lines
signals this state is called ON, for
serial data lines are called
SPACE is used.  Between levels -3...+3 V
there is a dead zone, causing
catching receiver hysteresis: state
The line will be considered changed
only after crossing the corresponding
th threshold (see figure below).  Levels
signals at the transmitter outputs should
be in the ranges -12...-5 V and +5...+12 V
to represent one and zero according to
responsibly.                              

  For the RS-232C interface there is a special release
receiver buffer chips (with
hysteresis) and bipolar transmitters
th signal.                              

   Receiver Transmitter              

     1489 1488                 
     ---- ----                 
    +-++--+ +-++--+               
  1A+1++14+VCC VEE+1++14+VDD A|B*|Y    
  1C+ +4A 1A+ +4A -+--+---  
  1Y+ +4C 1Y+ +4B 0|0 |VDD  
  2A+ +4Y 2A+ +4Y |  |     
  2C+ +3A 2B+ +3A 0|1 |VDD2Y+ +3C 2Y+ +3B |  |     
 GND+7 8+3Y GND+7 8+3Y 1|0 |VDD  
    +-----+ +-----+ |  |     
                               1|1 |VEE  

  Transmitter:                            
  A - RS-232 input, C - hysterical control
rez (TTL), Y - output.                
  Receiver:                              
  A, B - TTL inputs, Y - RS-232, VDD output
p= +12 V, VEE = -12 V.                   
  Transmitter output status table: 
  * 1V=log.1