Track: By me composed! Xe-xe.. :)
Author: Macros, 14 July 2K1.
-----------------------------------------
FLASH-ПЗУ
DIP-32 TSOP-32
+-+----+ +-+---+
Vpp+1 32+Vcc A11+1 32+OE#
*A16+ +WE# A9+ +A10
*A15+ +PR#* A8+ +CE#
A12+ +A14 A13+ +DQ7
A7+ +A13 A14+ +DQб
A6+ +A8 PR#+ +DQS
A5+ +A9 WE#+ +DQЧ
A4+ +A11 Vcc+ +DQЗ
A3+ +OE# Vpp+ +GND
A2+ +A10 *A16+ +DQ2
A1+ +CE# *A15+ +DQ1
A0+ +DQ7 A12+ +DQO
DQO+ +DQб A7+ +A0
DQ1+ +DQS A6+ +A1
DQ2+ +DQЧ A5+ +A2
GND+16 17+DQЗ A4+16 17+A3
+------+ +-----+
PLCC-32
A12 A15* A16* Vpp Vcc WE# PR#*
-+---+----+----+---+---+---++
/ 4 3 21 32 21 30|
A7+5 29+A14
| o |
A6+ +A13
| |
A5+ +A8
| |
A4+ +A9
| |
A3+ +A11
| |
A2+ +OE#
| |
A1+ +A10
| |
A0+ +CE#
|13 21|
DQO+ 14 20 +DQ7
+--+---+---+---+---+---+---+--+
DQ1 DQ2 GND DQЗ DQЧ DQS DQб
TSOP-32 TSOP-40
+-+---+ +-+---+
A11+1 32+OE# A16+1 40+A17
A9+ +A10 A15+ +GND
A8+ +CE# A14+ +NC
A13+ +DQ7 A13+ +A19*
A14+ +DQб A12+ +A10
PR#+ +DQS A11+ +DQ7
WE#+ +DQЧ A9+ +DQб
Vcc+ +DQЗ A8+ +DQS
Vpp+ +GND WE#+ +DQЧ
*A16+ +DQ2 PR#+ +Vcc
*A15+ +DQ1 Vpp+ +VccA12+ +DQO *WP#+ +NC
A7+ +A0 *A18+ +DQЗ
A6+ +A1 A7+ +DQ2
A5+ +A2 A6+ +DQ1
A4+16 17+A3 A5+ +DQO
+-----+ A4+ +OE#
A3+ +GND
A2+ +CE#
A1+20 21+A0
+-----+
TSOP-44 TSOP-48
+-+---+ +-+---+
Vpp+1 44+PR# A15+1 48+A16
WP/*A18+ +WE# A14+ +BYTE#
*A17+ +A8 A13+ +GND
A7+ +A9 A12+ DQ15/A-1
A6+ +A10 A11+ +DQ7
A5+ +A11 A10+ +DQ14
A4+ +A12 A9+ +DQб
A3+ +A13 A8+ +DQ13
A2+ +A14 NC+ +DQS
A1+ +A15 NC+ +DQ12
A0+ +A16 WE#+ +DQЧ
CE#+ +BYTE# RP#+ +Vcc
GND+ +GND Vpp+ +DQ11
OE#+ +DQ15/A-1 WP#+ +DQЗ
DQO+ +DQ7 NC+ +DQ10
DQ8+ +DQ14 *A18+ +DQ2
DQ1+ +DQб *A17+ +DQ9
DQ9+ +DQ13 A7+ +DQ1
DQ2+ +DQS A6+ +DQ8
DQ10+ +DQ12 A5+ +DQODQЗ+ +DQЧ A4+ +OE#
DQ11+22 23+Vcc A3+ +GND
+-----+ A2+ +CE#
A1+24 25+A0
+-----+
TSOP-56
+-+---+
NC+1 56+NC
NC+ +A16
A15+ +BYTE#
A14+ +GND
A13+ +DQ15/A-1
A12+ +DQ7
A11+ +DQ14
A10+ +DQб
A9+ +DQ13
A8+ +DQS
NC+ +DQ12
NC+ +DQЧ
WE#+ +Vcc
RP#+ +Vcc
NC+ +DQ11
NC+ +DQЗ
Vpp+ +DQ10
WP#+ +DQ2
*A18+ +DQ9
*A17+ +DQ1
A7+ +DQ8
A6+ +DQO
A5+ +OE#
A4+ +GND
A3+ +CE#
A2+ +A0A1+ +NC
NC+28 29+NC
+-----+
+========+----------+-------+----------+
|м/сх |орг-ция* |корпус |примечание|
+========+----------+-------+----------+
|28F256 |32K*8 BE |DIP-32 |2,3,30=NC |
+--------+----------+-------+----------+
|28F256 |32K*8 BE |PLC-32 |2,3,30=NC |
+--------+----------+-------+----------+
|28F512 |64K*8 BE |DIP-32 |2,30=NC |
+--------+----------+-------+----------+
|28F512 |64K*8 BE |PLCC-32|2,30=NC |
+--------+----------+-------+----------+
|28F010 |128K*8 BE |DIP-32 |30=NC |
+--------+----------+-------+----------+
|28F010 |128K*8 BE |PLCC-32|30=NC |
+--------+----------+-------+----------+
|28F010 |128K*8 BE |TSOP-32|6=NC |
+--------+----------+-------+----------+
|28F001 |128K** BB |DIP-32 |- |
+--------+----------+-------+----------+
|28F001 |128K*8 BB |PLCC-32|- |
+--------+----------+-------+----------+
|28F001 |128K*8 BB |TSOP-32|- |
+--------+----------+-------+----------+
|29EEO10 |128K*8 SA |DIP-32 |1,30=NC |
|29F010 | | | |
+--------+----------+-------+----------+
|29EEO10 |128K*8 SA |PLCC-32|1,30=NC |
|29F010 | | | |+--------+----------+-------+----------+
|29EEO10 |128K*8 ON |TSOP-32|6,9=NC |
|29F010 | | | |
+--------+----------+-------+----------+
|28F020 |256K*8 BE |DIP-32 |30=A17 |
+--------+----------+-------+----------+
|28F020 |256K*8 BE |PLCC-32|30=A17 |
+--------+----------+-------+----------+
|28F020 |256K*8 BE |TSOP-32|6=A17 |
+--------+----------+-------+----------+
|28F002BC|256K*8 BB |TSOP-40|12,13,45= |
|/BN/BL | | |NC |
+--------+----------+-------+----------+
|28F002BE|256K*8 BB |TSOP-40|13,45=NC |
|/BV | | | |
+--------+----------+-------+----------+
|28F0OCHBX|512K*8 BB |TSOP-40|12,45=NC |
|/BN/BL | | | |
+--------+----------+-------+----------+
|28F0OCHBE|512K*8 BB |TSOP-40|45=NC |
|/BV | | | |
+--------+----------+-------+----------+
|28F008BE|1024K*8 BB|TSOP-40|- |
|/BV | | | |
+--------+----------+-------+----------+
|28F200 |256K*8 |TSOP-44|2=WP#;3=NC|
| |128K*16 BB| | |
+--------+----------+-------+----------+
|28F200 |256K*8 |TSOP-48|16,17=NC |
| |128K*16 BB| | |
+--------+----------+-------+----------+
|28F200 |256K*8 |TSOP-56|19,20=NC |
| |128K*16 BB| ||
+--------+----------+-------+----------+
|28F400 |512K*8 |TSOP-44|2=WP# |
| |256K*16 BB| | |
+--------+----------+-------+----------+
|28F400 |512K*8 |TSOP-48|16=NC |
| |256K*16 BB| | |
+--------+----------+-------+----------+
|28F400 |512K*8 |TSOP-56|19=NC |
| |256K*16 BB| | |
+--------+----------+-------+----------+
|28F800 |1024K*8 |TSOP-44|2=A18 |
| |512K*16 BB| | |
+--------+----------+-------+----------+
|28F800 |1024K*8 |TSOP-48|- |
| |512K*16 BB| | |
+--------+----------+-------+----------+
|28F800 |1024K*8 |TSOP-56|- |
| |512K*16 BB| | |
+--------+----------+-------+----------+
|29F200 |256K*8 |TSOP-44|1,3=NC |
|29LV200 |128K*16 BB| |2=RY/BY# |
+--------+----------+-------+----------+
|29F200 |256K*8 |TSOP-48|13,14=NC |
|29LV200 |128K*16 BB| |16,17=NC |
| | | |15=RY/BY# |
+--------+----------+-------+----------+
|29F400 |512K*8 |TSOP-44|1=NC |
|29LVЧO0 |256K*16 BB| |2=RY/BY# |
+--------+----------+-------+----------+
|29F400 |512K*8 |TSOP-48|13,14,16= |
| | | | NC |
|29LVЧO0 |256K*16 BB| |15=RY/BY# |+--------+----------+-------+----------+
|29F800 |1024K*8 |TSOP-44|1=RY/BY# |
|29LV800 |512K*16 BB| |2=A18 |
+--------+----------+-------+----------+
|29F800 |1024K*8 |TSOP-48|13,14=NC |
|29LV800 |512K*16 BB| |15=RY/BY# |
+========+----------+-------+----------+
*BE - Bulk Erase (entirely erasable)
BB - Boot Block (asymmetrical blocks)
SA - Symetric Architecture (symbol blocks)
+==========+--------------------------+
|CE# |Sampling a microcircuit. |
+----------+--------------------------+
|OE# |Enable output buffers|
| |Low level at low |
| |CE# level allows reading|
| |data from the microcircuit. |
+----------+--------------------------+
|WE# |Enable recording. |
| |Low level at low |
| |CE# level allows recording|
| |and transfers output buffers|
| |in high-impedance state-|
| |independent of the signal |
| |OE#. |
+----------+--------------------------+
|DQx |Bidirectional bus lines |
| |data. |
+----------+--------------------------+
|BYTE# |Control signal for you- |
| |bora mode access to |
| |chips with 8/16-bit |
||organization. They have |
| |two 8-bit banks and their |
| |memory cells are addressed |
| |16-bit words. Low |
| |signal level BYTE# set-|
| |no 8-bit exchange mode |
| | lines DQO-DQ7, while |
| |line DQ15/A-1 becomes |
| |the youngest line address- |
| |sa, switching banks, and |
| |lines DQ8-DQ14 go to |
| |high impedance state|
+----------+--------------------------+
|Ax |Address bus input lines. |
| |Line A9 allows feeding |
| |12 V for reading the production code-|
| |driver (A0=0) and device- |
| |stva (A0=1), while on |
| | other address lines |
| |a logical "0" is supplied. |
+----------+--------------------------+
|RP# (PWD#)|Low level resets |
| | command register and translates |
| |chip in Deep mode |
| |Powerdown with minimal |
| | power consumption. Re-|
| |water signal in high log-|
| |whose level "awakens" |
| |microcircuit, after which it |
| | switches to reading mode |
| |data. Feed high |
| |(12 V) voltage allows|
| |programmingeven |
| |protected boot block. |
+----------+--------------------------+
|WP# |Record protection. At low |
| |WP# level modification |
| |Boot block or other blocks |
| |kov with the bit set |
| | protection is possible only with |
| |presence of 12 V at the RP# input. |
| |At a high level of protection |
| |blocks are ignored. |
+----------+--------------------------+
|RY/BY# |Ready signal (high |
| | level) microcircuits to |
| | next operation |
| | programming or |
| | erasing. Low level |
| | shows employment |
| |control machine you- |
| |completing the operation sti- |
| | injury or programming |
| |nia. The output is usually not |
| |controlled by OE# signals |
| |and CE#. In m/skh 28F01bSA and |
| |older output has type |
| |"open collector", |
| | lockable by command, and |
| |programmable assignment.|
+----------+--------------------------+
|3/5# |Signal switching |
| |mode of operation of m/skh depending on |
| |dependency from the supply voltage-|
| | zheniya, introduced for optimization |
|| performance improvements or |
| |consumption. |
+==========+--------------------------+
FLASH memory from Intel
Based on the organization of the array, there are micro-
circuit diagrams:
- Bulk Erase - erasing is possible only
for the entire volume.
- Boot Block - the array is divided into non-
how many blocks of different sizes can be erased?
regardless. One of the blocks has additional
proprietary hardware protection against
erasing and recording.
- Flash File - array section on non-
how many equal independently erasable
blocks are usually the same size, which
allows them to be called microcircuits with
symmetrical SA architecture.
First generation flash memory
First generation microcircuits (28F256,
28F512, 28F010, 28F020) have one-
byte organization (32K, 64K, 128K and
256K*8) and represent a single mass
memory, completely erasable and program-
worlded byte by byte. Access times are indicated -
appears at the end of the designation (for example,
28F010-65) and lies in the range of 65-200 ns.
Microcircuits of the first releases (1990) had
guaranteed number of erase cycles
-programming 10,000,modern -
100,000.
Erasing and programming flash memory
possible only when Vpp is applied to the input
voltage 12 V according to commands, recording
wash into an internal register in the bus cycle
recordings via WE# signal.
Command execution is initiated by writing
their codes in the internal register, I don’t have
specific address.
+========+------+----------+-----------+
|Command |Number |1st cycle | 2nd cycle|
| |cycles|buses | tires |
| |tires +---+--+---+---+----+--+
| | |R/W|A |D |R/W|A |D |
+--------+-----++--++-++--++--++---++--+
|Read | | | | | | | |
|Memory | 1 |W |X |00h|- |- |- |
+--------+-----+---+--+---+---+----+---+
|Read ID | 3 |W |X |90h|R |0(1)|Id |
+--------+-----+---+--+---+---+----+---+
|Set-up | 2 |W |X |20h|W |X |20h|
|Erase/ | | | | | | | |
|Erase | | | | | | | |
+--------+-----+---+--+---+---+----+---+
|Erase | 2 |W |EA|AOh|R |X |EVD|
|Verify | | | | | | | |
+--------+-----+---+--+---+---+----+---+
|Set-up | 2 |W |X |40h|W |PA |PD |
|Program/| | | | | | | |
|Program | | | | | | | |
+--------+-----+---+--+---+---+----+---+
|Program | 2 |W |X |COh|R |X |PVD|
|Verify || | | | | | |
+--------+-----+---+--+---+---+----+---+
|Reset | 2 |W |X |FFh|W |X |FFh|
+========+-----+---+--+---+---+----+---+
Here X denotes an inessential ad-
res, ID - manufacturer identifier or
device, EA is the address of the cell, in which
which controls erasure, EVD -
given, read during verification of cheese-
tions (must be FFh), PA and PD - address and
programmable cell data, PVD -
data read during program verification
framing.
Command assignment: Read Memory -
read data command translating
microcircuit into read mode, compatible with
interface with EPROM.
Read ID - command for reading identification
ditch In subsequent bus read cycles
at address 0 M_Id is read (identifier
manufacturer's code, 89h), at address 1 -
D_Id (device identifier, for micro-
circuit diagrams 28F256, 28F512, 28F010, 28F020 are
B9h, B8h, BChh and BDh respectively).
Set-up Erase/Erase - preparation and
actually erasing. Inner loop
erasing begins when the signal rises
WE# in the second bus cycle and ends
on the subsequent bus write cycle or
by internal timer (Stop Timer).
Erase Verify - erasure verification. B
difference from Read Memory, verifiable
cellplaced in more stringent conditions
readings to improve reliability
erasure control.
Set-up Program/Program - preparation and
actual programming. Team you-
is filled in the same way as erasing, but in
on the second bus cycle the address is transmitted and
programmable cell data.
Program verify - program verification
erasure (similar to erasure verification)
nia)
Reset - a reset command that interrupts the
programming or erasing command.
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