Iron - A short story about the capabilities of the processor Z-180.

<b>Iron</b> - A short story about the capabilities of the processor Z-180.


            Z-180.

music by Jaan _______________________________



 The proposed description is not intended to
precision reference. This is a discussion ideologues Z80/Z180 
line with positive function of designing computers. 

 Probably the most convenient for the reader
will be a representation in the form of a comparison with the
all familiar Spectrum'ovskim Z80
and describe a number of differences that, in fact, define the 
line of the family. The architecture of any computer (including

Spectrum'a) is closely related to the structure and
ideology of the processor. Development of hardware on any 
platform is closely associated with the development of this 
ideology. Exceptions to the author unknown. Therefore I would 
like to discuss here is conceptual features CPU Z180 with 
respect to Z80. 

 A bit of history. (If you can not wait -
scroll down this passage Ed.) Company
Zilog was founded by former employees
Company Intel (this fact has resulted in
Later in the litigation). Conventional wisdom is that they just 
wanted money. However, we can assume that this is true, but not 
all. Do not want to spawn another myth, and the following 
should be considered as an attempt to Possible reconstruction 
of what happened.  I. People working in the inner sanctum 
corporation, ie, - Have a real Know-how and can thus influence 
the conceptual aspects of the designed processors are rarely 
hurt money.

- II. Takes an entire team of extra-class, with the intention 
to establish his own firm. For such a monumental task requires 
not only money and Know-how, but having our own concepts of 
development of processors, m-k, otherwise the competition can 
not either with Intel, either with Motorola. Luchsche to 
understand the situation, recall that Intel and Motorola 
produce processors that are used respectively, in the family of 
PC computers and Macintosh. Probably the concept of 
microprocessors Intel - highly specialized devices that have 
concentrated extreme performance (productivity, the amount of 
addressable memory ...) - - Proved to be unacceptable for this 
group. With this approach, the computing power

identified with memory and proizvoditelnstyu, ie - Purely 
technical characteristics, without regard to peripheral issues, 
architectural requirements, process complexity and create 
Software, the complexity of the user interface. 

 The concept of Zilog: Moderate speed and volume of addressable 
memory. Specific difference is the integration of on-chip core 
architecture, understood a few wider than the actual processor. 
This manifested already in the Z80: a mechanism to support

regeneration process in memory (the output RFSH),
automatic application of clock cycles waiting
loop input-output. Foremost, at the time, clocking a one CLOCK 
sequence. Enhanced system commands, approximating the assembler 
to high level languages. Block the I / O and transfer 
equivalent macros processors of other firms. In Z180 deepen 
these trends. 

 1. Changing the clock mechanism.
The prehistory of the problem - that says Horwitz: "For 
example, for microprocessor I8080 (prototype Z80, domestic 
analog - 580IK80) requires three power supply and two coming 
from outside the clock signal with a level of 12c and precisely 
seasoned delay between them. Arising in connection with the 
inconvenience of the plant worked with the microprocessor 8080 
Designers in such traps as the notorious "problem of ticks, 
which accompanied the MITS Altair 8800, and (initially produced 
amateur mini-computers) and arose in cases where stringent 
requirements for the two clock input of the microprocessor, do 
not met soon enough. Several companies (rather than one IBM) 
advertised in amateur magazines kits designed to address 
"Problem bars." In those days we were glad everything worked. 
However, the designer of our day demand (and gain) is 
incomparably greater ease of use of microprocessors. " 

 In Z180 timing problem is solved in
more broadly than just the
reliability and reproducibility of the technological circuit 
solutions. Adopted in the Z80 agreement on reference delay 
times from the front input (CLOCK) is replaced by an agreement 
measure the time of the output signal Processor F. That is, in 
fact, the whole system Spectrum is not external but internal

clocking - the entire system is clocked
CPU. This allowed us to throw out the inevitable cycles of time 
delays and significant squeeze machine cycle time. From the 
point of view designer's Spectrum - architecture, this means a 
complete rejection of traditional computer synchronization in 
whole. By the way, having a moderate speed (eg 14 Mhz) can be 
waived by buffering the tire and getting extremely simple, 
cheap and technological nodes on the bus, because tolerances 
for the "collapse" signals on the bus on time, even increase. 
(Although, proektiuya synchronization system, we have to count 
them.) 

 2. Changing the concept of the machine cycle.
Architecture Z180 is no longer rigidly set (as in Z80). A 
designer can programmatically through the system software, to 
change the architecture of the nucleus. If given that Z180, in 
essence, is an architecture, rather than actual processor (a 
concentrated processing power), we can talk about expanding the 
range of opportunities and reconfigurable. In practice, this is 
as follows: In the Z80 refresh cycle hard, "let into" the cycle 
of M1 (recovery package operations). In Z180 regeneration cycle 
exists independently at full machine cycle. Frequency of 
occurrence of such cycles can be varied within wide limits, or 
just cancel. This will unify all the cycles on the bus

duration. (So-called "inner loops"
do not require sharing the bus, duration equated to beat.) The 
Z180 has been supported the idea of arbitrarily set the 
length of the signal IORQ. (In KAY256 TURBO It had to do with a 
special external circuits.) In the machine cycle there were 
additional signals - information and gating - they can be used, 
for example, to facilitate the sharing of RAM. 

 3. Extension mechanism of interruption.
Familiar to all Spectrum'istam group interrupt NMI / INT 
received priority levels 2-3. At level 1 nahoditsa so-called 
"TRAP" interrupt - interrupt incorrect code operation. This is 
exactly wherever will depart the program with

undocumented commands. Interrupt transfers control to 0-th 
vector. There is a special bit, allowing the processor to 
distinguish between "cold start" (at RESET) on the "hot" (for 
TRAP). Ie is the possibility of macro (which is equivalent to a 
macro of any reasonable size) "Blanks" aces programming 
Spectrum'a. There are still two feet, bearing obligations 
"bdit" (in addition to INT) - INT1 and INT2 (4-5). Ineetsya 
also has a 7-m pieces of interrupts that can request On-chip 
peripherals (timer, DMA, serial ports) with the lowest priority 
(6-12). 

 4. Expansion of the system commands.
Team SLP - spat.Protsessor falling asleep ...
MLT - multiplication of two eight-registers with the result in 
reg. pair: H * L -> result - in the HL. 17 cycles.

Three teams testing on the battery
 without destroying its contents.
Seven special teams to access internal devices Z180 (DMA, 
etc.). Teams expose 00h in the high byte address port.  A 
curious subtlety is that experts of firm Zilog vnutrichipnye

devices are called registers, but
Indeed - it's the same ports as corresponding cycles are 
identical. Therefore, if the program meets the traditional 
team, for whatever reason, that displays value to the port with 
zero high byte address, it risks falling into vnutrichipovye 
ports, the consequences of which are the most fun ...  For the 
programmer, these ports represent from a "bank" Long 40h, in 
the interval Long 100h. (8 th lowest bit addresses)

Bank can be placed in one of 4 places:


  00h

      0 Pre follows ustano0 3Fh vit current situation of the 
bank. 

  40h

      1 For RESET bank is put in "0"

  7Fh

  80h 5. Inland ports.

      2 They can be divided into
BFh a group of service (exchange with vnu1 C0h friction devices 
(half       3 algebra, DMA, and so on. ) And group

1 FFh architecture that define the configuration of the kernel 
and features vzaimodeistviya chip with the outside frame on the 
constructive hardware plan. There are registers that define the 
frequency timing, number WAIT'ov in IORQ, frequency

following regeneration. There is even a register, allowing 
changes to the logic of the bus and duration of the output 
edges of some signals. (Other than register a "double

appointment of "such a cell and can not be named). From the 
perspective of a programmer using such a register is very easy 
to make the program fail." authors, he conceived as a saving.


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  The above information are basic
for a family of Z180. Further development -
- Z180-> Z181-> Z180 given rekurentno.
Ie take the Z180, add something - we Z181. Take the Z181 and 
something else add - have a Z182, etc. For service supplements 
used "emptiness" in the bank 40h. (The situation is similar to 
the undocumented commands - the company leaves itself a 
foundation for the future, not reflected in those. 
documentation, but the open craftsmen and once this groundwork 
to float its hosts, putting an end to creativity, "folk art".)


              ___

 Readers were first ZF questions
by TR-R'u. A reader from Pskov, has decided that (C) Nemo has 
invented a new processor. Unfortunately, this landmark 
accomplishment we can not do. We are talking about a 
commercially available off-chip firm Zilog. Some readers agreed 
that the TR-R no later What tomorrow will be released in 
rodazhu. This is also not so. Ability to implement this idea

directly linked to market development Spectrum. If it is 
possible to de-monopolize, to create an effective structure

(Clubs, network), make the market ringing
transparent - then it becomes possible.
Major efforts are now directed specifically
in this direction - otherwise
This architecture is just hanging in the air. I would like to 
wish the programmer only support the well-established and 
generally accepted architectural components - a ensures that 
the platform of sharahanya and dispersion of efforts and 
resources (and ask the stable development of the vector), which 
is already there are not many, it is also impossible

and it will be split. At the moment,
author's opinion, such architectural components of a Turbo-mode 
and 256Kb memory. Machines with less memory and speed (1.43 - 
equal to laggards) vypuskatsya no longer.


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