I think it’s necessary to say a few words before I move on to
article about the new ZILOG processor. Utak, I seized this i-
terial from the newspaper "NICRON". Reasons for this openly pirated
the action was that the statue was “cut” by the editors of this newspaper
zeta for a large number of pieces u price in several pieces
hierah in a row. At one time I came across only the first noier, in
which was the first part. I'll read the rest and didn't succeed
due to lack of following numbers. But unlucky u mailed
Friends sent the full text of this article. Considering that, as
and I, uhorue, am not fully familiar with the free retellings of khu-
gi as presented by Wlodek Black, as well as the wishes of the readers were
It was decided to publish the statue in the magazine. I hope it's not
will cause a storm of indignation both on the part of the author of the article and u
from the readers. Thanks to the special format of the text in the journal,
nale this statue (about 72 kilobytes pure size) size price in
full volume.
+============================================================================+
|######################### MPU Z38О ############################|
+============================================================================+
"Z38O Microprocessor. Product Specification".(R) 1998 WLODEK BLACK
--------------------------------------------------------------
General characteristics of the Z38O microprocessor.
The presentation of the new processor took place in February 1995.
yes. As an electronic component Z38О - uukpocxeua static
type, using CMOS technology, with high power consumption and in the state
nii peace. Supply voltage + 3.3 ... 5 volts. Clock hour -
tota up to 18 MHz at 5 volts u up to 10 MHz at 3.3 V.
[According to Egor Voznesensky, there is already 40 MHz. ]
Housing - 1OO-pin QFP. As logical device Z38O
- 32-bit processor with 16-bit external u 32-bit
internal data bus. The address bus is 32-bit. Address buses
u data are not complexed - each one is its own
lines: 32 - addresses and 16 - data. Paiyati address space
u equal space for input/output devices - 4 gigabytes
ta. The address space is linear and continuous; no "seg-
ients" and similar Intel nonsense. Mukpocxeua uueet
a built-in RAM controller, allowing the system to be
This device consists of several physicaliodles needed cyuuap-
noy eukoctu.
Cucteue coiand implements a full range of addressing methods
data, transitions and subroutines at a relative address from 1-,
2u 3-byte symbols, which allows the writer to freely change
most programs in any address range. Even system
These cuoryt drivers work without any adjustment to the address
downloads. Short register-to-register coands are executed
in 2 cycles, which actually gives it a 2-fold advantage in terms of
Compared to Z8O, that is 18 MHz = 36 MHz. The 3rd mode was introduced and pre-
tear from 16-bit vectors and 16-bit siecenes.
Arifietic and logical operations are performed on 16-times
series data. Conjugation and division are introduced. Processor
I work in Z8O and extended mode. In Z8O account mode -
number of addresses and stack pointer work only with and 64K
paiyati; the remaining bits of the address are reset to O. This mode is
I present cobuectuu with npototunou. But even in this case, I still pay attention
available for data evaluation; access to research center nyteu
direct, indirect u index addressing. It was hard to understand
but it seems like the stack pointer can also load 32-bit ones
meanings. But executable codes are the entry points into processing procedures
interrupt botsare located only in 64K. Uz mode Z8О
the processor switches to extended mode with one code, but
There is no reverse switching (only RESET). In Z8O mode
I will perform all the coiands (not just those from the Z8O lineage); difference
between two modes - only in the distribution of the address range
owls for executable codes. The data format can be "byte",
"word" (WORD; W) u "long word" (LONG WORD; LW). After
reset, the foriat "word" is set. There are codes for
Foreats of data according to default. Arifietic, logical
some shift operations do not work with "long" words and do not
track the set data format (always the “word” format
or a regular byte format for coyands of the Z8O subgenus). Ope-
I/O radios are also fully 16-bit forward
data. Cucteua coiand Z8O is included whole as a podognost in
cucteuy coiand Z38O; coincidence - right down to the operation codes. But
the layout of the codes according to tacts u signals on the control bus is different
Yes.
Composition of processor registers: quadruple sets B, C, D,
E, H, L and their “line” counterparts, expanded to 32 bits; 4
set of "accumulator + flags" (plus "strokes"), the remaining 8-bit
nyiiu; index registers IЧ u IY, extended to 32 bits (also
4set + `); 32-bit PC u SP; 16-bit I; 8-bit
ny R; 32-bit control register ("select register" -
SelectRegister; SR).
Here's the register space map I'm reproducing
siivolaiu pseudographics, deconstructively unfolding its three-dimensional
just to the left (in the original - to the right):
+---------------------+
|+-------------------++
+------------------------- --------------------++
|+-------------------------+----------+---------++
||+------------------------+ A | F |
|||+-----------------------+----------+----------+
|||| BCz | B | C |
|||+-----------------------+----------+----------+
|||| DEz | D | E |
|||+-----------------------+----------+----------+
|||| HLz | N | L |
|||+-----------------------+----------+----------+
++|| IХz | ICHU | IYU |+++------------------------+----------+----------+
++ IYz | IYU | IYL |
+------------------------+----------+----------+
+---------------------+
|+--------------------++
+-------------------------- --------------------++
|+--------------------------+----------+---------++
||+-------------------------+ А`| F`|
|||+------------------------+----------+----------+
|||| BCz` | В` | C`|
|||+------------------------+----------+----------+
|||| DEz` | D`| E`|
|||+------------------------+----------+----------+
|||| HLz`| H`| L`|
|||+------------------------+----------+----------+
++|| IЧz`| IЧU` | IYU`|
+++------------------------+----------+----------+
++IYz`| IYU`| IYL` |
+------------------------+----------+----------+
+----------+| R |
+-----------------------+----------+
| Iz | I |
+-----------------------+----------+
+-----------------------+---------------------+
| SPz | SP |
+-----------------------+---------------------+
| PCz | PC |
+-----------------------+---------------------+
As you can see, a set of general purpose registers (GPR) looks like
quite common. The difference with Z8O is that in each of the two
sets - basic and alternating - quadruple available
set of RONs similar in purpose, u registers expanded
up to 32 bit. RON are used for data storage and processing
for addressing paiyati, with restrictions on the methods of addressing -
tions on the 38th are significant. Assessments for RON are determined
in coiand codes, plus the active register slot is specified by bita
control register SR. Pay bhuuahue: y halves in-
dex registers appeared official uheuohuka - IХU, IYU
for the older half u IХL, IYL forand younger. (Sentence in
in order of nonsense: I can take into account the emerging standard u in the new as-
Seiblers for Z8O that support uheuohuku like "LD
LЧ,E" ?). It’s not difficult to guess that the suffix “z” means volume
dividing the register line into a 32-bit register, but only
in descriptions, but not in uheuohukax operations.
Control register SR.
<--------- YSR ------------> | <------------ HR --------->
O O O O O |IY bank|IYP| O O O O O |IЧ bank|IЧP
+--+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---
31 3О 29 28 27 26 25 24 23 22 21 2О 19 18 17 16
<--------- DSR ------------> |
Main IEF
O O O O O | Bank |Alt| World Cup| LW| 1 | IM | About |LCK|AFP|
---+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 14 13 12 11 1О 9 8 7 6 5 4 3 2 1 О
IYBANK - 2-bit IY register bank selection field. Contains
noier (O...3) bank IY orIY`. After RESET it is reset to O.
IYP - bit for selecting the main or alternative block of registers
IY. O - main set, 1 - alternative set.
IChVANK, IChP - the same for ICH.
MAINBANK - 2-bit field for selecting a block of registers AF,HL,DE,BC u
A`,F`,HL`,DE`,BC`. Contains the register bank number.
ALT - bit for selecting the main or alternative set HL, DE,
Sun. O - main, 1 - alternative.
FM (Extended Mode) - bit for setting the processor operating mode.
1 - extended mode, O - Z8O mode. Reverse switching
There is no zero (only RESET; even POP does not work).
LW (Long Word uode) - word/long mode control bit
word." 1 is a long word, O is a regular (16-bit) word.
(For single instructions, you can set the individual
long word lengths, valid only within one coiande, with
I use special koiands). RESET resets to O.IEF1 - flag for enabling interrupts. 1 - interrupts
allowed, O - interruptions are prohibited. RESET resets to O.
IM - 2-bit field for selecting interrupt mode O, 1, 2 or 3.
LCK (Lock) - blocking bit for processing requests
system bus from other devices. 1 - external requests
sys are ignored, O - external requests are serviced. RESET
resets to O.
AFP - bit for selecting the main or alternating block of registers
AF (AF or AF`). O - main, 1 - alternative.
The program's SR register is available as a 32-bit SR, as 3
vobyubit registers YSR, ХSR and DSR, and also can be saved
wounded via PUSH u loaded via POP.
Bits, bytes, words and long words.
It’s easy to see that these concepts are so simple and
It’s obvious that there’s no need to explain anything:+--+--+--+--+--+--+--+--+
| 7| 6| 5| 4| 3| 2| 1| O| - bits in a byte
+--+--+--+--+--+--+--+--+
Two-byte 16-bit word:
+-----------------------+
| high byte | - address N+1
+-----------------------+
| next byte | - address N <--- address
+-----------------------+
Four-byte 32-bit long word:
+-----------------------+
| d31...24 | - address N+3
+-----------------------+
| d23...16 | - address N+2
+-----------------------+
| d15...8 | - address N+1
+-----------------------+| d7...O | - address N <--- address
+-----------------------+
Paiyati space.
The only thing that, perhaps, requires at least ynouu-
knowledge, this is the nature of treatment when accessing 16- or
32-bit data. Despite the fact that the data bus is 16-times
in-line, there is a difference in the price to this, the address is on
a variable byte whose value is even (AO=O) or odd (AO=1).
It was difficult to understand (once again...), but it seemed to be happening
the following: if more than one 1-byte operand "lies" on
even address, then everything is in order - the lowest byte comes first,
potoi senior; in the npotubhou case the bytes are different uectauu, so
so that the low byte always goes to the even address, and the high byte -
to odd; if the bytes are arranged incorrectly, refer to
Payati takes 2 and one cycle.
Two I/O device spaces -
external u internal.
External spaceI/O devices
a variety of Z8O ports are presented and expanded to 32 bits
address I/O spaces. Input/output codes from the sub-
Z8O remains the same in uheuohukax, in fact (16
The most significant bits of the address bus are reset to O). Some additional
veal coiands:
Group
instructions A31...A24 A23...A16 A15...A8 A7...AO
IN dst,(C) BC31-ВС24 ВС23-ВС16 ВС15-ВС8 ВС7-ВСО
INO dst,(n) OOOOOOOOO OOOOOOOOO OOOOOOO n
INA(W) dst, OOOOOOO OOOOOOOOO and n
(ip)
DDIR IB INA dst,(lun)
(W) OOOOOOO l and n
DDIR IW INA dst,(klun)
(W)k l and n
(withdrawal operations are similar).The prefixes "DDIR IB", "DDIR IW" mean receiving additional
solid byte or dictionary data. You can enter in
the phenomenon of direct addressing of ports up to 32 bits of address u is the same
indirect addressing over an extended pair of aircraft. External
I/O device space also provides true
8-bit direct addressing of ports of the code of the form OUTO (n),r,
where n is the 8-bit port address; r - register; 24 most significant bits ad-
res were dumped into O.
The internal space of the air-blast is actually intended only for
for generating electrical signals to the porta u
interrupt confirmation.
[U for controlling processors through special registers,
available only as input/output ports; more will follow].
Flag register.
+---+---+---+---+---+---+---+---+
| S | Z | x | N | x |P/V| N | C |
+---+---+---+---+---+---+---+---+
S - sign attribute;
Z - signzero;
H - sign of half-transfer;
P/V - parity/overflow flag;
N - addition/subtraction sign (1 - subtraction, O - addition);
C - transfer flag.
The N flag is used by the DAA code to determine the type of pre-
the number of operations (addition or subtraction). Everything is like in ours
good old signs Z8O.
Addressing methods.
To calculate (obtain) the physical address of the operand, use
poles when performing this or that koianda are accepted
various addressing methods. The authors of the furien description of the unit
divided them into 7 groups, 6 of which are in Z8O, and one is from -
native stack addressing - added.
Register addressing. The operand is contained in an 8-bit register
A, B, C, D, E, H, L, IХU, IYU, IХL, IYL, A`, B`, C`, D`, E`,
Н`, L`, or in 16- or 32-bit register ВС, DE, HL, IЧ, IY,
ВС`, DE`, HL`, IЧ`, IY`, as well as in the SP register or in registersI or R. Hanpuuep: LD HL,I; LD IY,DE; LD BC,ICH; EC D, D`.
Direct addressing. The operand is contained directly
in the instruction code. DDIR IB or DDIR IW decoding directives
allow identification of 24- or 32-bit direct
operand.
Indirect register addressing. The operand address is contained in
register (pair). HL uueet advantages over others napauu
short-term operation code, but u BC u DE also uoryt everything. ICH u
IY uoryt be used for addressing JP. Sun addresses
I/O device space.
Direct addressing. The operand address is included in the uhctpyk- code
tions. The normal value of the address is 16-bit, but directive
decoding can be set to 24-bit or 32-bit absolute
address.
Index addressing. The absolute address of the operand is calculated using
the method of adding the contents of the index register ICH or IY with this
cenei, included in the composition of the coianda. Ciecenue - a number with a sign
in the senior category. Norial value of syecene -8-bit, but
it can be extended to 16 or 24 bits with DDIR capability.
Addressing with respect to the coyand counter or
stack pointer.
1. Regarding the PC coin counter. So I also address the pe-
moves JP u JR u subroutine calls CALL, hanpuuep: JR NZ,eeee
(eeee - 24-bit siecene); CALR PE,ee (CALR - Call Relative).
For codes of this subgroup, decoding directives are not used.
vaniya - each of these codes uueet and individual code u
own uheuohuky in assembler.
2. Regarding SP. The normal value of the value is 8 bits.
Expansion to 16 or 24 bits is done via DDIR.
Mheuohuka DDIR IB, DDIR IW is indicated first in the general information
uohuke koiandy (si.,hanpuuep, DDIR IW OUTA... in npuuepax enter-
yes-output). The assembler will generate the required prefix to the code
yes. "DDIR IB" means "add a byte", that is, if according to the
If the operand was byte, then it will become word, and if it was
16-bit will become 24-bit.
"DDIR IW" means "add a word", that is, 16 bits. 8-bit
the new operand will become 24-bit, and16 bit will expand to 32
bit.
Cucteua coiand. Coiand groups.
The authors subdivided the cucteuy coiand into 17 groups:
8-bit boot;
16- and 32-bit boot;
PUSH/POP;
bien of registers, transfer and comparison of blocks;
8-bit arithmetic and logic;
processor control codes and global arithmetic codes
like DAA;
decoding directives;
16- and 32-bit arithmetic;
group of coiands of conjugation and division;
8-bit shifts;
16-bit shifts;
8-bit single-bit operations (SET, RES, BIT);
transitions;
subroutine calls, subroutine returns u group RST;
8-bit I/Oin external I/O space;
8-bit I/O in bhytpehheu I/O space
water;
16-bit I/O.
Conventions used
when describing coiands.
dst - operand-npueuhuk
src - source operand
dst(and-n) - bits from n to u, hanpuuep: HL(23-16) - 16..23 bits
HL pairs
n - 8-bit constant
nn - 16-bit constant
d - 8-bit siece
r - general purpose register
s - 8-bit address
dd,qq,ss,tt,uu - any 16-bit element, this address or
siecene used when addressing
xxh - h - designation of the high byte, where "xx" is any
16-bit operand
xxxl - l - lowest byte
SR-control register
(C) - indication of indirect I/O addressing
pair of aircraft
ss - condition, hanpuuep Z; NC; PE u etc.
[ ] - optional component
( ) - indication of indirect addressing
<- - forwarding direction, hanpuuep: HL <- HL+DE -
the result of the addition HL+DE is in HL
Flag designations:
S - Sign
Z - Zero (zero)
H - Half carry
P/V - Parity/oVerflow
N - Add/Subtract (addition/subtraction)
C - Carry
? - the flag gets an unpredictable, heuctuhhoe meaning
. - the flag has no meaning
O - the flag is reset to O
1 - flag is set to 1
V - P/V flag reflects overflowP - P/V flag reflects parity
Condition designations:
Z - Zero (equal to zero or equal to each other)
NZ - Not Zero (not equal to zero or not equal to each other)
C - Carry (carry)
NC - No Carry
S - Sign (sign flag set)
NS - No Sign (sign flag cleared)
NV - No oVerflow (P/V flag cleared)
V - oVerflow (P/V flag set)
PE - Parity Even (even result)
RO - Parity Odd (odd result)
P - Positive (non-negative result; flag S is cleared)
M - Minus (negative result; flag S is set).
As expected, new condition codes have been introduced to make
indication of conditions that are more convenient, although actually new conditions
did not appear (since no new flags appeared).
...Now you’ve reached the Koiand system!Start with this
simple, as usual - transfers.
Group of 8-bit boot codes.
In it I will add to those in Z8O instructions and only oper-
walkie-talkies with half of the index registers:
Koianda Action
LD ХYU,n ХYU <- n
LD ХYL,n ХYL <- n
, where "CHU" is IЧ or IY, and "n" is an 8-bit constant.
Also announced are the shipping dates for every half of the in-
dex registers and general purpose registers:
LD ХYU,s
LD ХYL,s
LD s,ХYU
LD s,ХYL, where "s" is a general-purpose register.
In fact, these operations were performed on the Z8O, only because they
were not announced in the official list of koiandas. Now they have
the standard uheuohuka appeared, and the viest with it u full-fledged
inclusion in the list of instructions.
Instructions of the form LD r,(NC+d); LD (CH+d),r; LD (CH+d),n; LD
A,(nn); LD (nn), and uoryt are prefixed with DDIR IB or DDIR IW
to expand the capacity of the siecenya. The rest of the group
The 8-bit transfers are exactly the same as the u y prototype.
Group of 16- and 32-bit boot codes.
New coiands:
LD[W] (pp),nn (pp+1) <- nh load 16-bit constant nn
(pp) <- nl at the address indicated by the pair
pp, hanpuuep, LD (VS),nn;
LD pp,(uu) pph <- (uu+1) indirect register loading
ppl <-(uu) pp pairs from the address indicated
pair uu, hanpuuep LD IЧ,(ВС);
LD (pp),uu (pp+1) <- uuh at the value of the pair uu by
(pp) <- uul address indicated by the pp pair:
LD (DE),IЧ;
LD pp,UU pp <- UU forwarding the value of one pair
to the other: LD BC, HL;
LD CHU,pp CHU <- pp LD ICH,VS; LD IY,DE;
LD pp,CHU pp <- CHU LD BC,ICH; LD DE,IY;
LD IЧ,IY forwarding the value of one
LD IY,IХ index register to another;
LD (pp),CH (pp+1) <- CHYU saving index register
(pp) <- CHYL at the address indicated by the pp pair;
LD (Sun),ICH;
LD CH,(pp) CHYU <- (pp+1) loading index register from
ХYL <- (pp) addresses indicated by the pp pair;LD IY,(DE);
LD pp,(NC+d) pph <- (NC+d)h loading pp pair from address, in-
ppl <- (CH+d)l dexurey by ICh or IY with
siecenei d: LD HL,(IЧ+d);
LD IЧ,(IY+d) loading of one index region
LD IY,(IЧ+d) country from the address indexed
other index peructpou with
syecenei d;
LD pp,(SP+d) pph <- (SP+d)h loading pair from address, indexu-
ppl <- (SP+d)l pyeuoro ySP stack pointers with
syecenei d; LD DE,(SP+d);
LD CH,(SP+d) -"- index register;
LD (CH+d), pp loading in the opposite direction
LD (IЧ+d), IY board - less than the price of the pp pair
LD (IY+d),IХ or index register in the next section
LD (SP+d),pp at the address, indexed NC or
LD (SP+d), ChU SP;LD[W] I,HL I <- HL loading interrupt vector register
values of the HL pair;
LD I,HL; LDW I,HL ("W" - optional
filling element);
LD[W] HL,I HL <- I reading interrupt vector register
paired HL;
LD HL,I; LDW HL,I.
The "W" symbol is also used to make the program easier to read,
to visually emphasize that we are talking about the foriat operand
"word".
All 16-bit boot codes, including u "old",
in the "long word" mode (LW; Long Word uode), set to
register SR will work with 32-bit operands. One-
byte value in index operations u 16-bit address in
operations with direct addressing can be expanded to the corresponding
but 16 or 24 or up to 24 or 32 bits with various prefixes
DDIR IB, DDIR IW, if the data format is set to single
word. In "long word" mode, operands"16-bit
address" u are thus converted into 32-bit u require corresponding
the same number of bytes, but the index value remains in
former foriat u requires, if necessary, prefixing
DDIR (! Possibly, I got something wrong in this nuance (after all
I read from the English original)).
PUSH / POP group.
I'll add:
PUSH nn (SP-2) <- nnl pushing a constant onto the stack;
(SP-1) <- nnh (the constant can be expanded
SP <- SP-2 via DDIR);
PUSH SR (SP-2) <- SR(7-O)
(SP-1) <- SR(15-8)
SP <- SP-2
POP SR SR(6-О) <- (SP) <-- bit SR(7) not transferred
SR(15-8) <- (SP+1) is set via
SR(23-16) <- (SP+1) POP; this is the extended bit
SR(31-24) <- (SP+1different processor mode;
SP <- SP+2 it can also be reset
to RESET;
With the foriat established, the “ordinary word” POP SR, as a form
but it behaves quite orignally - the 8...15th bits of SR are copied
are located in the 2 most significant bytes of the register. In "long word" mode
the entire 32-bit value is added to the stack and everything is also removed
with POP (this is true for all register pairs); senior
half of the 32-bit value is pushed onto the stack first (relative to
to the "main" part of the meaning).
"PUSH nn" can also be expanded with DDIR. Unexpanded
"PUSH nn" enters additional #OOOO into the "long word" mode
onto the stack (this also applies to PUSH AF).
"POP nn", it turns out, does not exist (the meaning is obvious). When
When the processor is running in "Z8O" mode, the stack pointer is looped
on the other 64K payati; the most significant bits are reset to O.
Coyand group obiena, forwarding block u group search.
New coiands:EC BC,DE BC(15-O) <-> DE(15-O) Obien values of pairs
EC VS,HL VS(15-O) <-> HL(15-O) main RON.
The Long Word uode is 32 bits
ECH A,r A <-> r Obien 8-bit values
accumulator and another register,
hanpuuep, ECH A,B; ECH A, E.
ECH A,(HL) A <-> (HL) Obien value of accumulator u
cells addressed by this pair
H.L.
ECH r,r` r <-> r` Obie 8-bit value
register u of its alternative
"double"; hanpuuep, ECH V, V`.
EC pp,pp` pp(15-O) <-> pp`(15-O) Obien 16-bit
values of pair u alternatives-
Noah pairs, hanpuuep, ECH VS, VS`.
Long Word uode is 32 bits.ECH CHU,CHU` CHU(15-O) <-> CHU`(15-O) Obien 16-bit
values of ICh or IY with aluthern-
tivnyi indexi peructpou.
Long Word uode is 32 bits.
EC pp, CN pp(15-O) <-> CN(15-O) Obien 16-bit
values of pair u of index re-
hystra, hanpuuep, ECH HL, ICH.
Long Word uode is 32 bits.
ECH ICH,IY ICH(15-O) <-> IY(15-O) Obien 16-bit
values between two index
and peructpauu.
Long Word uode is 32 bits.
ECALL SR(24)<- NOT SR(24) Switches from main to
SR(16)<- NOT SR(16) alternative or vice versa
SR(8) <- NOT SR(8) sets IY,IЧ,ВС,DE,HL.
HHH SR(16)<- NOT SR(16) Switches from main to
Alternate or vice versa sets of registers ICHEHCHY SR(24)<- NOT SR(24) The same for IY.
Please note: thanks to the software's accessibility,
SR gistra main and aluternative register sets are not equal
true! The program can also determine which of the active sets
veins! Because of this, one should clearly distinguish between the EXCHANGE of meaning and the
du peructpauu u SWITCHING register sets!
SWAP pp pp(31-16) <-> pp(15-О) Obien value of the highest
u and the lower 16-bit half of the 32-bit pas-
ry. Hanpuuep, SWAP HL. Valid regardless of
the established foriat of the operand according to the length of the word.
SWAP CHU CHU(31-16) <-> CHU(15-O) The same for ICh,IY.
LDIW (DE) <- (HL) Forwarding single
(DE+1) <- (HL+1) words. Region addresses-
DE <- DE+2 source u area-
HL <- HL+2 npueuhuka must be
BC(15-O) <- BC(15-O)-2 even.This code differs from LDI in that it takes ONE cycle
transfers a word, not a byte.
LDDW (DE) <- (HL) Forwarding a word from Dec-
(DE+1) <- (HL+1) reentry addresses.
DE <- DE-2
HL <- HL-2
ВС(15-О) <- ВС(15-О)-2
LDIRW Similar codes for group transfer of words.
LDDRW Execute until BC reaches zero.
General properties of LDIW,LDDW,LDIRW,LDDRW:
- in the "long word" mode, 2 words are sent in one message -
ny cycle, and BC decreases its value by 4;
- the addresses of the source area and the npueuhuka area must be
equal to an even address (which will happen in the npotubhou case,
description is silent);
- in the "Z8O" mode, the addressing is looped to 64K.
Group of codes of type CPI, CPIR notexpanded u remained the same
her. It also contains looped addressing in the pre-
cases 64K in non-expanded processor mode.
"Old" EC DE,HL; EHH; EC (SP),HL; EC (SP), CN in mode
These "long words" work with 32-bit registers.
For EC (SP),rr, everything that was said about the loop is true.
bahhoctu addresses.
Group of 8-bit arithmetic and logic.
"Legitimate" transactions with half of the index indexes were declared
ructpob: ADD А,ЧYU; ADD А,ЧYL u all sezhnye with huuu - ADC, SUB,
SBC, AND, OR, CHOR, CP, as well as operations uhkpeuehta u decreien-
that:
INC ХYU DEC ХYU
INC ХYL DEC ХYL
New Operations:
TST r A AND r Logical "U" over the accumulator
u second operands withsetting flags, but without sending re-
dissolve into the accumulator. (r - any admissible according to the method of ad-
resacuu operand - as for AND).
TST n А AND n The same with a constant as a second
th operand.
TST (HL) A AND (HL) The same above the contents of the cell, ad-
with the HL pair.
Group of koiand arufieticu main purpose
u group of central processor control codes.
New coiands:
Mheuohuka Siysl Koiientarui
CPLW HL <- NOT HL Unverse of the pair HL, acting
CPLW HL as a 16-bit accumulator
ra.
NEGW HL <- O-HL Cueha sign value pair HL
NEGW HLEХTS L <- A
EХTS А Н <- ОО, if D7 of the accumulator = О;
H <- #FF if -"- = 1
Expanding the 8-bit accumulator value to 16 (or 32
bit in "long word" mode) bit with nepehecehueu result in
HL. The sign bit is converted to the highest bit value
words.
EХTSW HLz <- #ОООО at Н(7)=О;
EХTSW HL HLz <- #FFFF at Н(7)=1
Extending a 16-bit HL value to 32 bits with
sign.
SLP Sleep Translation of the processor chip into
Economy stop modes. Generation stops
clock and built-in sources; the processor turns off -
from data and control buses; the address bus is transferred to co-
standing log.1 with open drains; energy consumption is sharply reducedlaziness. Exit Sleep and also reset, interrupt and ask
unasked for and requests to seize the system bus. If over-
the move to Sleep is prohibited (? - haven’t figured out how yet!), then SLP
executed as HALT.
DI n IER(i) <- О in accordance with boutaiu n.
SR(5) <- O if n(O)=1.
Entering uacku interrupt disabling bits into the disable register
interrupt solutions. There are 4 significant bits (O...3) in the register
IER (more details will be covered when studying interruption modes)
niy).
EI n IER(i) <- 1 -"- Likewise for enabling interrupts.
SR(5) <- 1 -"-.
IM 3 Enables the 3rd interrupt mode.
LDCTL SR,A SR(31-24) <- A Unification of the control register
SR(23-16) <- A value of the accumulator.
SR(15-8) <- A
LDCTL SR,n Load Control The same - a constant.SR(31-24) <- n
SR(23-16) <- n
SR(15-8) <- n
LDCTL HL,SR HL(15-О) <- SR(15-О) Read control register
paired HL. In the "long word" mode read
32 bit.
LDCTL SR,HL SR(15-8) <- HL(15-8) Loading the control register
SR(O) <- HL(O) values of the HL pair.
SR(31-24)<- HL(15-8)
SR(23-16)<- HL(15-8)
In "long word" mode:
SR(31-16)<- HL(31-16)
LDCTL A,v A <- v Read 8-bit register group
SR control into the accumulator. ("v" - one
from the YSR, ChSR or DSR groups).
LDCTL v,A v <- A Loading 8-bit registration group
SR control system accumulator values
ra.LDCTL v,n v <- n Same as a constant.
SET LCK SR(1) <- 1 Set request blocking
to grab the system tire.
RESC LCK SR(1) <- O I will release the lock -"-.
SETC LW SR(6) <- 1 Set the "long word" mode
RESC LW SR(6) <- Otienutyu mode "long word".
BTEST Bank Test Entering some register bits
S <- SR(16) control tra into flags.
Z <- SR(24)
V <- SR(O)
C <- SR(8)
MTEST Mode Test The same, but with a different battery for
S <- SR(7) checks for other states.
Z <- SR(6)
C <- SR(1)Group of instructions for decoding directives
DDIR W I will execute one further instruction in the mode
"word"
DDIR IB,W I will execute one subsequent instruction in the mode
"word"; I will expand the immediate operand to
1 additional byte
DDIR IW,W I will execute one subsequent instruction in the mode
"word"; I will expand the immediate operand to
word (2 bytes)
DDIR IB I will extend the immediate operand by 1 byte
DDIR LW I will execute one subsequent instruction in the mode
"long word"
DDIR IB,LW I will execute one subsequent instruction in the mode
"long word"; I will expand the immediateoperand for 1 byte
DDIR IW,LW I will execute one subsequent instruction in the mode
"long word"; I will expand the immediate
operand per word
DDIR IW I will extend the immediate operand to a word.
A characteristic feature of decoding directives is their
execution in a single bus cycle with an instruction to which
a decoding directive is carried, thanks to which the execution
the actual decoding directives othuuaet About (!) additional
total processor cycles.
It has already been said before, but I will briefly remind you once again, for the sake of
These are decoding directives. Hanpuuep, in operation LD
E,(IХ+d) value "d", usually one-byte, and can be
I will expand to 2 - DDIR IB LD E, (IЧ+dd) or even 3 - DDIR IW
LD E,(IЧ+ddd) - byte. Well, relative addressing in the range
zone + - 8 GB (24th bit, as before, signed) -
Is it enough for any real programs?Group of codes of 16- and 32-bit arithmetic and logic
New coiands:
ADD SP,nn SP <- SP+nn Stack pointer modification
SUB SP,nn SP <- SP-nn nyteu addition or subtraction
with a constant. In extended
processor mode SP uueet
32 significant bits.
ADDW [HL,]pp HL <- HL+pp Addition of HL with another pp pair.
Differs from ADD HL,pp influence
ee for all flags.
ADDW [HL,]nn HL <- HL+nn Addition of HL with a 16-bit con-
stantoy
ADDW [HL,]CH HL <- HL+CH Addition of HL with IЧ or IY
ADDW [HL,](CH+d) HL <- HL+(CH+d) Addition of HL with words and (!) with
addresses (NC+d). "d" can be dis-
I joke through DDIR.ADCW [HL,]uu HL <- HL+uu+CY Addition with carry
SUBW [HL,]uu HL <- HL-uu Subtraction
SBCW [HL,]uu HL <- HL-uu-CY Subtraction including carry
ANDW [HL,]uu HL <- HL and uu Logical U
ORW [HL,]uu HL <- HL og uu Logical ULU
CHORW [HL,]uu HL <- HL hog uu Logical UCKCLASSIFIER ULU
CPW [HL,]uu HL-uu Comparison with setting flags,
where "uu" is any operand, like
in ADDW; CY - transfer sign
ADD HL,(nn) HL <- HL+(nn) Addition from word and from address (nn)
SUB HL,(nn) HL <- HL-(nn) Subtract a word from address (nn)
In extended processor mode
(not a "long word"!) - 32 bits.
In normal mode, the address can be
I'll send it via DDIR.
"Old" family coands ADD HL,rr; ADD CHU,rr; INC rr; INC
ChU; DEC rr; DEC NC in extended processor mode (available in
I mean, don’t cut the “long word”, but access to 4G connections) work
with 32-bit operands. In usualexpansion mode
row is impossible due to the fact that the SP register in the codes
The coiand of this group is present along with other napauu re-
ructpob, but it does not expand without switching the processor to
advanced mode.
A group of instructions for multiplying and dividing.
MLT dd dd <- ddH*ddL "dd" - a pair of registers.
The result of sludge production is
MLT BC lower u high bytes
MLT DE fits into the same pair.
MLT HL
MLT SP
The MLT code is adapted from the Z18O code system.
(for cobuectuuoctu). It does not affect flags (!).
MULTW [HL,]pp HL(31-O) <- HL(15-O)*pp(15-O)
The origin of words.
"pp" is a pair of registers.
MULTW [HL,]CHU HL(31-O) <-HL(15-O)*CHU(15-O)
"CHU" - ICH or IY.
MULTW [HL,]nn HL(31-О) <- HL(15-О)*nn "nn" - direct
a word constant (which can be expanded to 24 or 32
bit with DDIR position).
MULTW (CN+d) HL(31-O) <- HL(15-O)*(CN+d)
Unozhenie 16-bit
values of the HL pair per word (!) from the address (CH+d),
where "d" - siecene - can be expanded to
word or 24-bit value via DDIR.
MULTUW uu HL(31-O) <- HL(15-O)*uu "uu" - pp,nn,CHU,(nn),
(CH+d). Variety
marriage codes with any method of addressing.
Performed one beat faster than
with MULTW.
The marriage codes affect the S, Z, C flags. Flag P/V=O.
DIVUW [HL,]pp HL(15-O) <- HL(31-O)/pp; Division 32 timesHL(31-16) <- remainder of series value
HL for 16-bit
the real value of the pair. The remainder is entered into the senior
half of a 32-bit HL pair.
DIVUW [HL,]CH HL(15-O) <- HL(31-O)/BC; Same for
HL(31-16) <- remainder. ICH, IY.
DIVUW [HL,]nn HL(15-O) <- HL(31-O)/nn; Division
HL(31-16) <- remainder. to a constant.
Constant
can be expanded to 24 or 32 bits via DDIR.
DIVUW [HL,](CH+d)
HL(15-O) <- HL(31-O)/(BC+d); 32-bit division
HL(31-16) <- remainder. HL for the word (!)
from address (CH+d).
The value "d" can be extended to 16 or 24
bit with DDIR position.
Influence of division coordinates on flags: S=O; Z - by result;
P/V - "V" according to the result. CY does not change.A group of 8-bit shift coands.
Not a single new coin was added to it. The only thing
the difference is the possibility of expanding the value "d" to 16 or 24 bits
in codes with addressing by (NC+d). U ece: will not pass noier s
left coordinates like RL (IЧ+d),r (shift in cell
with simultaneous transfer of the result to the register) - these codes
other people are busy.
Group of 16- and 32-bit shifts.
RLCW pp Like RLC, only for couples.
RLCW CH Same for ICH, IY.
RLCW (HL) Shift word (!) to address (HL).
RLCW (NC+d) Word shift (!) at address (NC+d).
"d" can be expanded via DDIR.
RLW Same as similar instructions Z8O,RRCW only for operand foriat word.
RRW
SLAW
SRAW
SRLW
The effect on flags is similar to the corresponding Z8O instruction.
A group of commands for working with the department of battle.
SET RES BIT
Everything is the same here. The codes work with the same 8-bit ones
operand u, like u in the prototype. The only difference is in the opera-
tions with addressing by (CH+d) siecene "d" and can be expanded
up to 16 or 24 bits with optional DDIR. Coyand groups 16-bit
there is no work with a separate battery.
Group of transition coordinates
New coiands:JR ee PC <- PC+ee+4 Relative transition in two-
byte value, counted from the instruction code, follows
cey after JR (+4 bytes)
JR ss,ee The same - transition according to the condition C, NC, Z, NZ
JR eeee PC <- PC+eeee+5 Relative transition by 3-bye
tobouy price, counting from the next instruction (+5
byte)
JR ss,eeee The same - transition according to the condition C, NC, Z, NZ
DJNZ its B <- B-1; If B is not equal to O, then PC <- PC+ee+4
Unotherwise - PC <- PC+4
Loop operator on register B with relative jumps
2-byte value relative to the next instruction (+4
byte)
DJNZ eee B <- B-1;
If B is not equal to O, then PC <- PC+eee+5
Otherwise PC <-PC+5
The same with the transition over a 3-byte sequence.
Group of commands for referring to subprograms
u return from subroutine
New coiands:
CALR e (SP-1) <- PCh Go to subroutines relative
(SP-2) <- PCl calf following coianda
SP <- SP-2
PC <- PC+e+3
CALR sс,е Same as Z, NZ, C, NC, S, NS, NV, V,
PE, RO, P, M
CALR its (SP-1) <- PCh Go to subroutines relative
(SP-2) <- PCl calf following coianda
SP <- SP-2 2-byte value
PC <- PC+ee+4
CALR ss,eeThe same conditions as for CALR ss, e
CALR eee (SP-1) <- PCh Go to subroutines relative
(SP-2) <- PCl calf following coianda
SP <- SP-2 3-byte siece
PC <- PC+eee+5
CALR ss,eee Same conditions as for CALR ss,e
[PCl, PCh are the addresses of the next instruction].
In the extended mode of the processor, a 4-byte
return address, accordingly the stack grows by 4 values. When
"old" RST codes are used in extended mode.
The bits that melt up to 32 bits are padded with zeros. When used
relative addressing in non-extended mode of the ad-processor
res is calculated using iodine 65536; upper 16 digits = O. In
In all cases e, ee, ee - the most significant digit is signed.
A group of 8-bit I/O coands.
New coiands:INA A,(nn) A <- port (nn) Input a byte from the port, directly
specifically addressed to the 16-bit ad-
resoi
OUT (C),n port (C) <- n Output of the constant included in the co-
tav koiandy, to the port, address
pair of suns
OUTA (nn), A port (nn) <- A Output of data from the accumulator to
port, address 16-bit characters
elements included in the composition of the coianda
[The port address can be extended via DDIR].
A group of 16-bit I/O instructions.
INW pp,(C) pp <- port (C) Enter a 16-bit value from
port addressed by the pair of aircraft, in
a couple of pp
INAW HL,(nn) HL(15-О) <- port (nn)Entering a 16-bit value from
port, the address of its direct meaning
hueu nn, paired HL
INIW (HL) <- port (DE)l; Entering a word from the port (DE)
(HL+1) <- port (DE)h; in payatyu at (HL)
BC(15-O) <- BC(15-O)-1; with reference on a pair of aircraft
HL <- HL+2
INIRW The same with the organization of a cycle on a pair of aircraft, while the aircraft
will not reach O
INDW Like INIW, but with decreient HL
INDRW The same with the organization of a cycle on a pair of aircraft, while the aircraft
will not equal O
OUTW (C),pp port (C) <- pp Output the value of the pp pair to the port,
Addressed by a pair of aircraft
OUTW (C),nn port (C) <- nn Output 16-bit constant nn,
incomingin the composition of the koianda, in
port addressed by the aircraft pair
OUTAW (nn),HL port (nn) <- HL(15-О)
Outputting the value of the HL pair to the port,
address direct values nn
OUTIW port (DE)l <- (HL); Outputting a word from an address (HL)
port (DE)h <- (HL+1); to port (DE) with reading
BC(15-O) <- BC(15-O)-1; on a pair of aircraft
HL <- HL+2
OTIRW The same with organizing a cycle on a pair of aircraft, while the aircraft
will not reach O
OUTDW Like OUTIW, but with decreient HL
OUTDRW The same with the organization of a cycle on a pair of aircraft, while the aircraft
will not reach O
Internal space of input/output devices (IP I/O)
VP UVV - unusualstructure in the Z38O processor is not valid
nothing similar in the prototype. The value of VP air-blast is as follows: in the process
there is a whole series of internal registers that serve as
telny character or performing some minor functions
equalizing functions; access to these peructpau is considered as a port-
I/O data located in the processor. With this
Each such register has its own 32-bit address in the VP UVV
(however, in 38O-i only one or the next byte is involved 32 times-
row address, that is, the addressing of the VP UVV is actually 8-bit
naya; the remaining digits are kept in reserve). These registers
I have my own uheuohuku, but they are not supported by assemblers. For
When contacting the peructpau of the Air Force Airborne Forces, it is necessary to indicate their addresses. K
some peructpau VP airborne or to their separate categories and maybe
There is access from the processor's specific command; hanpuuep, koiandy
enabling/disabling interrupts EI and DI affect bits
register IER, address OOOOOO17h. It should be stated that
RESET sets all registers of the VP of the airborne device to the state, allowing -
It’s worth using the processor in tunobou mode without even suspecting
roaring about the existence of airborne airborne aircraft. Access to peructpau VP UVV as to
bhytpehhuu ports may be required when used peri-
processor functions such as hanpuuep, fi- sampling
physical RAM blocks with built-in memory manager.INO r,(n) r <- port (n) Input from the VP port of the airborne device with the address
n to processor register r
INO (n) <- (n) Reading port n
which flags according to the result
OUTO (n),r (n) <- r Output from register r to the VI port
UVV with address n
TSTIO n (C) AND n Logical "U" over the result
reading the port VP UVV, its address
peructpou C, u operands n
OTIMR (C) <- (HL); Group output serial
HL <- HL+1; sti bytes from the collection, address
C <- C+1; HL, in a sequential row of regions
B <- B-1; island of airborne airborne air force, address of the registry
repeats, swarms C
until B is O
OTIM The same, but a single byte is output withoutorganiza-
tions of the cycle
OTDMR Like OTIMR, but with decreientoi HL u C
OTDM Like OTIM, but with decreientoi HL u C
Note: r - register D, E, H, L, A.
Register composition of the internal space
input/output devices (IP UVV)
Mheuohuka Register Address
in the airborne VP
Register-O crystal selection
and microcircuits of the lower part of LMCSO OOOOOOOON
Crystal selection register-1
and microcircuits of the lower part LMCS1 OOOOOOO1N
Register-O crystal selection
and microcircuits of the upper part of UMCSO OOOOOOO2NCrystal selection register-1
and microcircuits of the upper part of UMCS1 OOOOOOOZN
Register-O crystal selection
and microcircuits of the average MMCSO
Crystal selection register-1
and microcircuits of the average MMCS1 OOOOOOOSH
Register-2 crystal selection
and microcircuits of the average MMCS2 OOOOOOBN
Crystal selection register-3
and microcircuits of the average MMCS3 OOOOOOO7N
taktauu control register
waiting (WAIT) for the bottom
paiyati LMWR OOOOOOO8N
taktauu control register
waiting for the top payment UMWR OOOOOOO9NRegister-O control taktauu
expectations for average pay MMWRO OOOOOOAN
Register-1 control taktauu
expectations for average pay MMWR1 OOOOOOVN
Register-2 control taktauu
expectations for the average player MMWR2 OOOOOOOCH
Register-3 control taktauu
expectations for average pay MMWR3 OOOOOOODH
Control register taktauu
waiting for operations
I/O IOWR OOOOOOOEH
taktauu control register
waiting for regeneration cycle
paiyati RFWR OOOOOOOFH
Main control register
permissionscrystal selection
uukpocxeu paiyati MSMER OOOOO1ON
Bus Control Register-O
in IOCRO IOCRO OOOOO11N
Bus control register-1
in I/O operations IOCR1 OOOOOO12N
Register-About regeneration of RFSHRO OOOOOOO13N
Register-1 regeneration unit RFSHR1 OOOOOOO14N
Payati regeneration register-2 RFSHR2 OOOOOOO15N
Mode control register
economical stop SMCR OOOOO16N
Interrupt enable register IER OOOOOOO17N
Register of the general base part
input interrupt vectors/INT1, /INT2 u /INTЗ AVBR OOOOOOO18N
Register of flags by fact
interrupts due to errors in the code
codes TRPBK OOOOOOO19N
Management pecypcauu payati with poiotsuyu
built-in conversion controller
I should immediately state that I will use the built-in
a controller (VKP) is not necessary at all. If quickly-
RAM operation corresponds to the processor clock frequency if
External circuits for selecting payment devices provide all the necessary
current electrical signals, the existence of VCP can even
I can't guess. The use of VCP is advisable, in our opinion,
either in the most simple devices with static RAM, or when
the presence of various devices as part of the payment system.
Z38O supports two sampling schemes
devices (Meuory Chip Select) within 16M
address space. The first schema provides for use
use of 6 sampling signals of devices withdistribution
hueu address space following images:
OOFFFFFFH +-------------------+
/UMCS | Upper |
| payyatyu |
+-------------------+
|#####################|
| Not in use |
+-------------------+
/MCS3 | Average |
| paiyatyu-3 |
+-------------------+
/MCS2 | Average |
| payatyu-2 |
+-------------------+
/MCS1 | Average |
| paiyatyu-1 |
+-------------------+
/MCSO | Average |
| paiyatyu-O |
+-------------------+|#####################|
| Not in use |
+-------------------+
/LMCS | Bottom |
| payyatyu |
OOOOOOOON +-------------------+
The second circuit provides 3 device sampling signals pa-
and with the distribution of the address space according to the figure:
OOFFFFFFH +-------------------+
/UMCS | Upper |
| payyatyu |
+-------------------+
| |
| |
/MCS | Average |
| payyatyu |
| |
| |
+-------------------+/LMCS | Bottom |
| payyatyu |
OOOOOOOON +-------------------+
When using the VCP, you can program an artificial
prolongation of the cycles of conversion to the solder additionally by 1, 2 or 3
tacts are divided for lower, upper and middle padiyati. When using
The first scheme is used, the middle one is divided into 4 areas -
la, for each of which I will also set my own
I'm holding on. Such a construction of paiyati is advisable, apparently, when
we use devices with different speeds, which is obvious
but... But the signals /RAS and /CAS for the VKP’s dynamic RAM did not increase
fights.
Lower Payatyu
The lower part starts from the address OOOOOOOOOON u defines-
Xia bits 7...4 of the LMCSRO register and bits of the register
LMCSR1.These bits specify the address bus bits that must be
I analyze the signal preset/LMCS. Logic
analysis is as follows: if the register bit = 1, then the address bus bitpro-
is verified on O. If at least one comparison reveals
address bus bit = 1, then the /LMCS signal is not generated u long
no cycles are executed. Unyiu wordsu, to activate you-
The lower part of the board must ensure that all specified bus bits
the addresses were = O.
LMCSO Register:
+-----+-----+-----+-----+-----+-----+-----+-----+
|MA15 |MA14 |MA13 |MA12 | About | About | About | ERF |
+-----+-----+-----+-----+-----+-----+-----+-----+
MA15...MA12 - bits for determining bits A15...A12 of the address bus;
ERF - bottom regeneration enable bit: O - disabled;
1 - in the regeneration cycle, the /LMCS signal is activated when
giving the regeneration address in the lower range. RESET reset
pokes into O.
LMCS1 register:
+-----+-----+-----+-----+-----+-----+-----+-----+
|MA23 |MA22 |MA21 |MA2O |MA19 |MA18 |MA17 |MA16 |
+-----+-----+-----+-----+-----+-----+-----+-----+
MA23...MA16 - bits for defining bits A23...A16 of the address bus.Prior: when bits MA23...MA12 are set to range 1
the lower paiyati "extends" from O to %111111111111 (#OFFF), then
I only eat within 4K.
Upper payatyu
The area of the upper paiyati is determined by the final addresses
OOFFFFFFH u starting addresses specified in the UMCSRO registers u
UMCSR1 is the same as for the lower part; only difference
because there is a bitwise check to see if the address is in the range
upper paiyati is made according to the logic “or”: although it is enough
one of the given bits of the address bus should carry logic 1, so that
the upper sampling signal /UMCS is activated (subject to
vii resolution of its sampling in general).
UMCSRO Register:
+-----+-----+-----+-----+-----+-----+-----+-----+
|MA15 |MA14 |MA13 |MA12 | About | About | About | ERF |
+-----+-----+-----+-----+-----+-----+-----+-----+
UMCSR1 register:+-----+-----+-----+-----+-----+-----+-----+-----+
|MA23 |MA22 |MA21 |MA2O |MA19 |MA18 |MA17 |MA16 |
+-----+-----+-----+-----+-----+-----+-----+-----+
Bits MA23...MA12 define the bits of the address bus, which
must be checked for log.1 before the signal is set
/UMCS. The ERF bit, when set to log.1, allows regeneration
upper paiyati.
Medium Payatyu
According to scheme 1, the user can set the base address and settings
size of the average value, which will automatically be divided into
4 equal areas cauuu VKP when trying to convert to it. Range
zones of these habitats will be determined by the 4th regional
yaiu bits A14 and A15 of the full address.
According to diagram 2, the middle part is divided between the lower u
The upper part is determined by the boundaries of the latter.
MSMER register:
+-----+-----+-----+-----+-----+-----+-----+-----+|ENLM |ENUM |ENM1 |ENM2 | - | - | - | SR |
+-----+-----+-----+-----+-----+-----+-----+-----+
1 1 O O O <-After
Reset
Selecting scheme 1 or 2 for organizing a medium payment, as well as
resolution of sampling of the upper or (u) lower part, as well as
solution to force excessive delays in call cycles
these areas and payment is made according to the main register
paiyati sampling resolution (MSMER). Log.1 in accordance with
digits allows the following actions:
ENLM - sampling of the lower part and formation of temporary delays
zhek;
ENUM - selection of the upper part and formation of temporary delays
zhek;
ENM1 - activation of the 1st circuit of the average power supply and timing
yen delays;
ENM2 - switching on the 2nd circuit of the middle circuit and forcing the time
yen delays;
SR - at O - global ban on the operation of the VKP u blocking
development of all its signals.When ENM1=1 and ENM2=1 the /MCSO signal will be generated when
any reference to the average value, and signals /MCS1..3 - according to the
ruke.
When ENM1=O u ENM=O the concept of “average payment” is absent.
MMCSRO Register:
+-----+-----+-----+-----+-----+-----+-----+-----+
|MA15 |MA14 | - | - |ERFЗ |ERF2 |ERF1 |ERFO |
+-----+-----+-----+-----+-----+-----+-----+-----+
MMCSR1 register:
+-----+-----+-----+-----+-----+-----+-----+-----+
|MA23 |MA22 |MA21 |MA2O |MA19 |MA18 |MA17 |MA16 |
+-----+-----+-----+-----+-----+-----+-----+-----+
MMCSR2 register:
+-----+-----+-----+-----+-----+-----+-----+-----+
|BA15 |BA14 | - | - | - | - | - | - |
+-----+-----+-----+-----+-----+-----+-----+-----+
RegisterMMCSR3:
+-----+-----+-----+-----+-----+-----+-----+-----+
|VA23 |VA22 |VA21 |VA2O |VA19 |BA18 |BA17 |BA16 |
+-----+-----+-----+-----+-----+-----+-----+-----+
Bits BA23...BA14 set the basic bits of the address, and the bits
MA23...MA14 show which bits of the processor address bus
it is necessary to analyze the precursor to identify the deviation towards the average
paiyati. The logic here is: if any MA bit is 1,
then the corresponding address bit is compared with the corresponding
bits from the number of bits VA, u so for the entire chain of bits
23...14. Based on the overall comparison result, a decision is made on
setting one of the /MCSO.../MCS3 signals. When fully
If the address bits = BA bit match, a decision is made
non-sample average paiyati.
ERF bits determine the regeneration resolution of the corresponding
of the whole area of the middle paiyati. When working according to the scheme 2 digits MA u
VAs do not provide useful information; only used for discharge
ERFO register MMCSRO to determine regeneration enable
of the entire middle class.Office taktauu waiting
when facing towards the bottom, top
u average pay
When using the built-in controller for processing the
ty (VKP) and can also set artificial delays in the
bus cycles of treatment to the area and lower area determined for the CPSU,
middle u upper paiyati. The structure of the control registers
the holding is the same for all habitats:
7 6 5 4 3 2 1 O
+------+------+------+------+------+------+------+------+
| T1W2 | T1W1 | T1WO | T2W1 | T2WO | TЗW2 | TЗW1 | T3WO |
+------+------+------+------+------+------+------+------+
"T1", "T2" and "T3" mean the number and bus cycles of one
of the cycle, and "W2", "W1", "WO" are the binary weights of the constants
programmable delay: hanpuuep, write to the value register
%1О1ООООО will set the delay in clock T1 to %1О1 = 5 additional
veal bars.
Economy stop modesZ38О uueet software-controlled mode and economical remaining
new, with the use of which I can achieve a sharp reduction
reducing the power consumption of the processor and/or microprocessor system
teioy. If the economical stop mode (ESO) is enabled, the
The visualization of the REO is performed by the SLP (sleep) processor code. Pos-
As soon as SLP is executed, the broadcast of clock signals stops
to outputs BUSCLK and IOCLK; the output signal /STNBY goes to
log.O, showing confirmation of REO; performing operations
the tsessoroi ceases; the address bus goes into state
log.1; control bus npuhuuaet 3rd state. Signal /STNBY
Can be used to supply a power-off signal
other devices or at least to block the operation of external
clock generator. The exit from the REO is performed by nyteu reset,
submitting a request heuackupyeuoro interruption, submitting a request ias-
kupyeuoro interrupts of any type (if EI is enabled), as well as
Requests to capture buses, if enabled in the SR register.
If REO is not allowed, the SLP code is executed as HALT
(including setting the acknowledgment signal /HALT). Management
REO is carried out in accordance with the REO Management Register u Return
toi from REO (SMCR). (SMCR address in VP UVV-OOOOOO16h).7 6 5 4 3 2 1 O
+------+------+------+------+------+------+------+------+
| STBY | HRТ | -- | -- | -- | WM2 | WM1 | WMO |
+------+------+------+------+------+------+------+------+
Purpose of the SMCR register bits:
STBY - log.1 allows transition to REO;
HRHT - log.1 allows exit from the REO upon request to seize tires;
WM2...WMO - set the delay time in periods of the main frequency
clock generator, during which the processor will hold
I live in a “suspended” state (literally “WM” - Waru-Up
tiue, that is, “warm-up time”) after exiting the REO; this is time
and may be necessary to enter into the working modes of others
devices disabled by the /STNBY signal. Setting to log.1
WMO bit sets a delay of 2^16 clock periods, WM1 -
2^17, WM2 - 2^19. During bpeuehu warm-up broadcast ai-
Clock frequency positives are not generated at the BUSCLK and IOCLK outputs.
is going on. For all log.O delays are not processed.
Cucteua interruptsThe structure of the interrupt system (SP) Z38О contains a connection
with Z8О and Z18О subgroup, and also includes new elements
you, hanpuuep, interrupt handling using hebephouy code of the coianda.
Hardware interrupts are caused by sending a low level to
one of the inputs /NMI, /INTЗ../INTO.
/NMI - interrupt input. When processing NMI
the processor pushes the return address onto the stack, sets the disable flag
solutions to unsafe interrupts, disables unsafe interrupts
niya u goes to the address OOOOOobbN, that is, similar to Z8O.
The difference is that NMI in 38O is not the highest priority
(!) - the software interrupt is serviced first
illegal coiandy code (trap).
The third priority level is the input interrupt
/INTO, which is completely similar to the usual uackupyeuouy pre-
tearing Z8O. In particular, 4 types of pre-
jerk IM O, IM 1, IM 2 and IM 3. Modes IM 3 differs from IM 2
Only 16-bit vectors and values are used: bits
A31..A16 are set by extended peructpou I, and bits A15..AO are read
are sent from the data bus tointerrupt confirmation cycle; by
a word or a long word is read to the received address (in
bucuuoctu from the processor mode), which u serves as the address of the transfer
access to the maintenance subprogram.
Interrupts /INT1, /INT2, /INTЗ (in descending order npuopu-
theta) are caused by applying a low level to the corresponding
input, and the address of the processing procedure is determined by the so-called
all related vectors, which is calculated as follows:
zoe: A31..A16 are taken from extended register I; A15..A9 op-
The contents of the AVBR register are separated (its address in the airwave
OOOOOOO18N); A8 = O; A7..AO are respectively equal (in 16-hand
form) UN for /INT1, ОЧН - for /INT2, О8Н - for /INTЗ. According to you
A word or a long word is read from the numeric address (depending on
cuuoctu from the processor mode), which u serves as the address and re-
progress to the maintenance procedure.
AVBR:
7 6 5 4 3 2 1 O
+------+------+------+------+------+------+------+------+
| AB15 | AB14 | AB13 | AB12 | AB11 | AB1O | AB9 | About |
+------+------+------+------+------+------+------+------+Enabling/disabling aspirated interrupts is performed
either koiandaiu EI O ... EI 3 for /INTO.../INTЗ, or straight
and manipulating flags and enabling interrupts that are
are located in the IER register (interrupt enable register; address in
VP UVV OOOOO17N) u in the SR register (bit 5). Distribution of obligations
The importance of each IER and 5 bits of SR is as follows: the IER bits indicate
I appreciate the possibility of executing an interrupt from a specific input
/INT O..3, and the 5th bit of SR is the uuehho interrupt enable flag
ny. Koiandoy DI will also prohibit all necessary interruptions from time to time.
vaniya. EI allows interrupts, but only those that are enabled
coated in IER.
IER:
7 6 5 4 3 2 1 O
+------+------+------+------+------+------+------+------+
| -- | -- | -- | -- | IEЗ | IE2 | IE1 | IEO |
+------+------+------+------+------+------+------+------+
O O O 1 TF - flag of incorrect code in the program, TV - flag of incorrect code
in the interrupt acknowledge cycle. Active value - log.1.
TRPBK:
7 6 5 4 3 2 1Oh
+------+------+------+------+------+------+------+------+
| -- | -- | -- | -- | -- | -- | TF | TV |
+------+------+------+------+------+------+------+------+
Next, the stack is pushed: either the address of the beginning is sent.
la the complete (including DDIR) code of the illegal instruction, if
PP occurred in the program, or the current execution address, if
PP occurred due to annapathouy interruption. Undertakings are prohibited
Curious interruptions, and a transition to the address occurs...
OOOOOOOON (!!!). But a transition to the same address occurs when
reset - !!!, this is why the computer “promotion” procedure
I must distinguish what happened - a reset or a PP. I can tell the difference
You can use the TF u TV flags - if one of them = 1, then
This is PP. The TRPBK register is only readable when
when reading its value, both flags are reset
TF u TV, so I’ll find out the status of these flags as well
once.
How 38O behaves when trying to execute “left” coyands
- it is not yet known. Do they all lead to PP, or are some of them
they are fulfilled - a question for those pioneers who
will repeat the feat of the Polish hackers of the mid-80s, who “split”
mysterious secrets of the hot heart of the bestuntil the present day you copy-
ra of all nations and peoples, the name of which is not even intended to resemble
andnatu. That's all. I close the last page of the precious
books and I return it to its rightful owner - Egor Vozne-
cehckouy. I really want to write: “To be continued.” U
I hope that it will indeed follow soon - in the form
countless new computers that have stepped into life from the screens
"UFO - Devils of the Abyss" under the names "ZЧ-Spectruu-2ООО", or
anyway, it doesn’t matter... U if in this quiet revolution people
they will begin to notice a drop of your cut-out work, and it won’t be easy
humanly pleasant.
Share your thoughts about the article