Crazy hands - All about HDD IDE: Brief description of ports and bits.

                                         
     Brief description of ports and bits     
         Hard drive controller.         
                                         
(C) Slot & Co                            
(R) Valerij KozHevnikov                  
 (500:95/462.18@ZXNet)                 
-------------------------------------------------------
                                         
 AM - address marker               
 CRC,KCK - cyclic control code    
 HOST - control computer         
 ECC - error detection code        
                                         
   Structurally, the controller contains two
device: 512k RAM controller and controller
HDD. There is also a controller on the same board
HT keyboards, but it is absolutely independent here too
not described.                          
                                         
 #FCAF (out)  - configuration management
controller.                             
                                         
 bit 7,1  - the most significant bits that form the no-
video page measuresdisplayed in mode
640*200.                                 
 bit 0 - (=1) connection of the config port
walkie talkie RAM 512k.                          
 bit 4  - (=1) block reset port
controller configuration.                
 bit 5 - (=1) write and read blocking
all controller ports.                 
 bit 6 - (=1) hardware reset HDD.      
                                         
 #FDAF (out) - RAM configuration port.    
                                         
   I won’t give it in full, but the facts
You can technically have 4 independent 128 ma-
tires. That is, in any of the three lower segments
cops can be substituted by one of the four
three pages, and from address #C000 - any of
32 available.                          
                                         
        +---------+------------+        
 | Segment |  Pages |        
        +---------+------------+        
        |  #0000 | 0,8,16,24 |        
        |         |             |        
        |  #4000 | 5,13,21,29 |        
        |         |             |        
        |  #8000 | 2,10,18,26 ||         |             |        
        |  #C000 |   any |        
        +---------+------------+        
                                         
   Next is all about the screw. I’ll say right away: evil-
consume software/hardware resources
not worth it there. The screw parks the heads and moves
The engine is working on stopping/accelerating. Life
It won't do him any good. I'm basically a hardware guy
I ruled out a reset: I tore off the 1st contact from
train, and everything is OK.                       
                                         
+-----------+-----------+-----------+ 
|     |          IN |           OUT | 
+=====+==========+===========+ 
|#FDAF|Data register D8-D15 |         sweat used | 
|#FFAF|       sweat used |Data register D8-D15 | 
|#FEAF|Data register DO-D7 |Data register DO-D7 | 
|#F6AF|Error register |Pre-payment register | 
|#EEAF|Sector counter register |Sector counter register | 
|#E6AF|Sector Noier Register |Sector Noyer Register | 
|#DEAF|Cylinder Noier Register |Cylinder Noyer Register | 
|     | (low) | (low) | 
|#D6AF|Cylinder number register |Cylinder number register | 
|     | (high) | (high) | 
|#CEAF|Accumulator/Head Register|Registerdrive/head| 
|#C6AF|Status register |Coyand register | 
+-----------+-----------+-----------+ 
|#CAAF|Alternative Register |State Management on- | 
|     |status |accumulator | 
|#C2AF|Drive Address Register |      sweat used | 
+-----------+-----------+-----------+ 
                                         
   Data registers #FDAF, #FEAF, #FFAF
used when performing reading operations
writing/writing a sector in program mode
I/O  #FEAF register is not available,
until the read or write operation begins
pussy. Data transfer takes place 16 -
bit words.  When reading from a port
#FDAF bits D8-D15 of the register are read
HDD data. To read them correctly
you must first count the digits
D0-D7 (#FEAF port) HDD data register.
When recording, first insert D8-D15 into the port
#FFAF, then D0-D7 to #FEAF port.         
   When performing long read operations
I/records (when, together with the data,
CCC bytes are sent) 4 ECC bytes are sent
bytes, before transmitting the ECC bytes
Bit 3 "Data" is then set
request" status register.             
 * This method of data transmission is accepted
due to the fact that the word size for HDDIDE
- 16 bits, and the bus size is 8 bits. Therefore
one word of data is transmitted/received
two IN/OUT commands. However, to speed up
of input/output operations, port addresses
com are located in such a way that it is possible
INI/OUTI commands can be used.     
                                         
   For example, reading one word:        
                                         
        LD HL,BUFFER                
        LD Sun,#FEAF                 
        INI                              
        INI                              
                                         
   or entry:                           
                                         
        LD HL,BUFFER                
        LD Sun,#OOAF                 
        OUTI                             
        OUTI                             
                                         
 * The #OOAF address is taken due to the fact that
manda OUTI makes DEC B before forwarding to
port                                    
   Error register #FbAF (in) defines
HDD state after the operation.
The state of this register is valid:  
 - after executing the command, if set
The "Eggog" bit in the status register has been updated. 
 - after execution"diagnostics" commands
or after performing internal diagnostics
HDD ticks on system reset.           
   In diagnostic mode, register codes
errors are defined as follows:             
                                         
    #01 no error                      
    #02 microcontroller error         
    #03 Buffer RAM error            
    #04 ECC hardware error           
    #05 microprocessor error          
    #8x prepare a coffin, dig a fucking grave
        (HDD is faulty).                
                                         
The values of the error register bits after  
           execute the command:           
                                         
+-------+-------+------+-------+------+-------+------+------+ 
|   7 |   6 |   5 |   4 |  3 |   2 |  1 |  About | 
+-------+-------+------+-------+------+-------+------+------+ 
|   BBK |  UNC |   About | IDNF |  About |  ABRT | TONF | AMNF | 
+-------+-------+------+-------+------+-------+------+------+ 
                                         
 bit 0 - Data Address Mark Not Found - us-
is set during command execution
"read sector" if address marker
sector data not found after correct
th locationID of this sect
ra.                                      
 bit 1 - Track 0 Not Found - setting-
is only available in the "recalibration" command, if
Is there no track detected after 2048 steps?
0.                                       
 bit 2 - Aborted Command - sets-
when receiving the "Write" state from the HDD
fault", "Not seek complete", "Drive sweat
ready" or when a non-
valid command.  Reason for error
can be determined from the status registers
errors and errors.                           
 bit 3 - used (=0)                   
 bit 4 - ID Not Found - required digits
linder, head, sector cannot be
detected or an ECC error has occurred in
ID field.                     
 bit 5 - used (=0)                   
 bit 6  - Uncorrect Data - ECC error in
data field. Installed in case of non-
correctable error.bit 7 - Bad Mark Block - in identifier
The defective sector label has been detected.  
                                         
   Precompensation register  #FbAF (out)
was used to indicate the qi number
linder from which to perform
pre-compensation.  In modern models
precompensation is controlled by the accumulation itself
tel, so this register can be used
use for other purposes.           
   The sector counter register #EEAFcontains
lives the number of sectors for read operations
nia/records.   The value of this register
decreases by 1 when processing each
sectors.  1 sector transfer occurs
with a value of 1, with a value of 0 - 256 sec-
torov.  If, when performing a multisector-
there was a recording error during transmission or
reading the next sector, then transfer
stops, and in the counter register sec-
tori there is a number of sectors that
left after the error was detected. When
successful completion of the command contains 0.  
   The sector number register #E6AF contains
starting sector number for read operations
nia-records.  After processing each sec-
torus contentsis incremented. After
command completion contains the sequence number
of the processed sector or the number of the sec-
the torus in which the error occurred.         
   Registers low #DEAF and high
#DбAF  cylinder number bytes determine
cylinder for which the work will be performed
this command.                          
   Drive/head register#CEAF (in/
out) looks like:                          
                                         
+-------+-------+------+-------+------+-------+------+------+ 
|   7 |   6 |   5 |   4 |  3 |   2 |  1 |  About | 
+-------+-------+------+-------+------+-------+------+------+ 
|   1 |   About |   1 |  DRV | HS3 |  HS2 | HS1 | HSO | 
+-------+-------+------+-------+------+-------+------+------+ 
                                         
 bit 0-3 - binary code of the selected head
 bit 4  - select HDD, 0 - drive 0  
                       1 - drive 1  
 bit 5,6 - sector size:               
    00 reserve                         
    01 reserve10,512 bytes/sector.               
    11 reserve                         
 bit 7  - reserve                        
                                         
   Status register #C6AF (in) display-
Shows the current state of the HDD. The meaning of this
register is updated after execution
each team.  If the BSY bit is set
this register, then any access to the HDD
are disabled, and the values of the remaining bits are not
valid.   Reading this register
resets hardware interrupt IRQ14 (in
This circuit does not use this interrupt.
Yes).                                   
                                         
   Bit values:                       
                                         
+-------+-------+------+-------+------+-------+------+------+ 
|   7 |   6 |   5 |   4 |  3 |   2 |  1 |  About | 
+-------+-------+------+-------+------+-------+------+------+ 
|  BSY | DRDY |  WFT |  DSC | DRQ |  CORR | INCH | ERR | 
+-------+-------+------+-------+------+-------+------+------+ 
                                         
 bit 0 - Eggog -indicates that the previous
the current command ended with an error, and one
or some bits are setin re-
error hyster.  Used for fast
checks for successful completion of the command.
Resets when the command register is filled with
a new command is sent.                  
 bit 1 - Index - set to 1 when
every turn of the bag of pancakes. In modern times
not used in other models.             
 bit 2 - Corrected Data - indicates that
An error occurred while reading data, which
paradise was successfully adjusted by the apparatus
tour of the KCC. Correctable errors are not
increase multi-sector transmission.         
 bit 3 - Data Request - this bit shows-
indicates that there is a request for data exchange
with a sector buffer when executing commands
read-write. For this request you must
can read/write data to the buffer, in
depending on the command being executed. (in
given circuit, a bit similar to this (27th
connector pin) controls the /Wait signal
CPU Z80).                                
 bit 4 - Drive Seek Complete - indicated
It means that the heads have completed the search operation.
ka.                                      
 bit 5 - Write Fault - indicates non-
malfunction in the drive, or an attempt to use
complete the "write" command with incorrect
parameters.                             
 bit 6 - Drive Ready - set to 1
means the HDD is ready to perform co-
cunts.                                   
 bit 7 - Busy - defines the HDD state.
Set to 1 when executing commands
dy or diagnostics after a system reset
sa.  When this bit is set, no
other bits of the status register are not
are valid. The Busy bit must be there
checked before reading any register
condition.                               
                                         
   Command register #C6AF (out) uses-
to load the command being executed. Pe-
Before writing a command, you need to prepare
create a task file - Task File (write
necessary data to ports #EEAF, #E6AF,
#DEAF, #DbAF, #CEAF) when the HDD is
in the "not busy" state (Busy = 0). Completed
The command begins immediately, with
moment of writing to the command register.         
   Alternate State Register
#CAAF (in) contains the same information as
same as the main one. The difference is that read
Deleting the alternate register does not reset -
There is no installed interrupt IRQ14.  (B
IRQ14 is not used in this circuit).     
                                         
   State control register #CAAF
(out) contains three control bits:     
                                         
+-------+-------+------+------+-------+-------+------+------+ 
|   7 |   6 |   5 |   4 |   3 |   2 |  1 |  About | 
+-------+-------+------+------+-------+-------+------+------+ 
|       |       |      |      | HS3EN |  SRST | /IEN |      | 
+-------+-------+------+------+-------+-------+------+------+ 
                                         
 bit 1 - Interrupt Enable - enable bit
interruption from HDD to HOST. When this
bit active and drive selected, HOST
is interrupted.  The signal to HOST IRQ14 must
be resolved through a tristable buffer.
When this bit is not active or the HDD is not selected,
wound, the HOST IRQ14 signal will be high
key level. (In this circuit, this is an interrupt-
not used).                    
 bit 2 - Soft Reset - softwarereset
To reset the HDD, this bit must be set to
1 and then reset to 0.                  
 bit 3  - Heads 3 Enable - used
to enable selection of heads 8 to 15. 
                                         
   Drive address register #С2AF (in)
contains the head and drive numbers,
selected by the previous team.           
                                         
+-------+-------+------+-------+------+------+------+------+  
|   7 |   6 |   5 |   4 |  3 |  2 |  1 |  About |  
+-------+-------+------+-------+------+------+------+------+  
|       | /WTG | /HS3 |  /HS2 | /HS1 | /HSO | /DS1 | /DSO |  
+-------+-------+------+-------+------+------+------+------+  
                                         
 bit 0,1 - Drive Select - switch selection bits
the corresponding drive is 0 or 1.       
 bit 2,3,4,5 - Head Select - binary code
selected head.                       
 bit 6 - Write Gate - execution bit
write, active during a write operation.-----                  
                                         
    Brief description of HDD IDE commands.     
                                         
   Commands from Host are written to the register
#C6AF commands and are executed immediately.
Before writing a command to the #EEAF registers,
#E6AF, #DEAF, #DbAF, #CEAF must be formed
create a task file, which
contains the data necessary to perform
tion of the team. Command codes are given in table
face:                                    
                                         
+---------------------+------+----------------------------+ 
|                     |      |     Used registers | 
|    Koianda | Code +-----+-----+-----+-----+------+ 
|                     |      |#EEAF|#E6AF|#DEAF|#D6AF|#CEAF | 
+=======+=====+=====+=====+=====+=====+======+ 
| Internal | #9O |     |     |     |     |  D | 
|   diagnostics |      |     |     |     |     |      | 
|                     |      |     |     |     |     |      | 
| Foration | #5O |  Y |     |  Y |  Y |  Y | 
|  tracks |      |     |     |     |     |      | 
|                     |      |     |     |     |     |      | 
| Identification| #EC |     |     |     |     |  D | 
|  HDD |      |     |     |     |     |      | 
|                     |      |     |     |     |     |      | 
| Unification | #91 |  Y |     |     |     |  Y | 
| HDD parameters |      |     |     |     |     |      | 
|                     |      |     |     |     |     |      | 
| Recalibration | #1O |     |     |     |     |  D | 
|                     |      |     |     |     |     |      | 
| Reading Buffer | #E4 |     |     |     |     |  D | 
|                     |      |     |     |     |     |      | 
| Reading sector(s) | #2H |  Y |  Y |  Y |  Y |  Y | 
|                     |      |     |     |     |     |      | 
| Verification | #41 |  Y |  Y |  Y |  Y |  Y | 
|                     |      |     |     |     |     |      | 
| Positioning | #7O |     |  Y |  Y |  Y |  Y | 
|                     |      |     |     |     |     |      | 
| Write buffer | #E8 |     |     |     |     |  D | 
|                     |      |     |     |     |     |      | 
| Record sector(s) | #3H |  Y |  Y |  Y |  Y |  Y | 
|                     |      |     |     |     |     |      | 
| Sleep | #E6 |     |     |     |     |      | 
|                     |      |     |     |     |     |      |+---------------------+------+-----+-----+-----+-----+------+ 
                                         
  Y - register used.              
                                         
  D - in the #CEAF register (drive selection
and heads) only the choice on-
accumulator.                                
  X - low tetrad of read and write commands
writing sector.                            
    X = %OOlr                            
    l - is responsible for the long operation mode
tions.                                     
     l=0 - normal mode, executed
CRC or ECC functions.                     
     l=1 - long operation mode. Not you-
CRC or ECC bytes are processed,
does not check for errors in the data field -
sya. When reading/writing a sector, add -
4 bytes of user CCC.             
                                         
    r - repetition mode when an
nii errors.                              
      r=0 repetition allowed          
      r=1 repetition prohibited          
                                         
Internal diagnostics (#90) - performed
The internal diagnostics of the HDD is performed, according to
the end of which in the error register the form
The exit code is generated. If there are no errors,
exit code #01.                      
Formatting track (#50) - according to this
the command is written in the lower level format -
to the specified HDD track. Many people have
IDE drives track formatting pro-
is emitted when the technological device is turned on
mode.                                  
HDD identification (#EU) - according to this code
mande into the sector buffer the pass is read
disk port and a DRQ request is generated in the re-
status hyster.                        
Initializing HDD parameters (#91) -
with this command the HDD is configured to pa-
parameters set to the drive from the Host.
This command must be executed after
"reset" HDD.                            
 Recalibration (#10)  - by this command
HDD heads are installed on the 0th digit
lindr.                                   
 Reading the buffer (#E4)  - using this command
sets the DRQ request in the register
condition.  Host can read the contents
my buffers (256 words) via data registers
nykh.                                     
 Reading sector(s) (#2X)  - according to this code
the specified sector is read in seconds
tor buffer (usually 512 bytes). Andform-
A DRQ request is made. Host can read
buffer contents (256 words) via re-
data gis. The team may have tired
The l and/or r bits have been updated. Contents re-
gistra #EEAF indicates the number of counts
of the sectors to be read (if #EEAF = 0 then read
There are 256 sectors).  Contents re-
hyster #E6AF indicates the starting sector. 
 Verification (#41) - format is checked
the specified track.                       
Positioning (#70) - HDD heads
are installed on the specified cylinder.    
Buffer recording (#E8) - set
DRQ request in the status register, after
of this Host must send 256 words to the
res data registers.                     
 Record sector(s) (#3X) - set
A DRQ request is made in the status register, and
Host must send 256 words via re-
data gis. After this, these records are
are transferred to a magnetic disk. The team can
bits l and/or r must be set. Contents
my #EEAF register indicates the number of
number of sectors to be written (if #EEAF
= 0 then 256 sectors are recorded). Contains
Register key #E6AF indicates initial
sector.                                  
 Sleep (#E6) - parking holo
wok, stopping the pancake engine and moving
into low power mode.
Any other command interrupts the command
sleep.  In older models it does not support -
Xia.                                      
                  -----                  
                                         
      Addressing HDD IDE registers.       
                                         
   To address HDD IDE registers in
ZX-NEXT signals used:            
                                         
A5,A6,A7,A8,A9 - (selecting lines)
form the base address of the HDD registers.   
A10,A11,A12,A13 - (address lines) used
used when selecting HDD registers.     
                                         
/WR - strobe for writing data to registers.    
/RD - strobe for reading data from registers.  
                                         
   To select registers:                 
                                         
A5,A7,A9 = 1                             
A6,A8 = 0                             
                                         
   The status of other signals is shown in
table.+-----+-----+-----+-----+-----------------+-----------------+ 
| A1O | A11 | A12 | A13 | Read registers| Writing registers| 
|     |     |     |     |  by signal /RD |  by signal /WR | 
+=====+=====+=====+=====+====+===+ 
|  About |  About |  About |  About |      #C2AF |        - | 
|  About |  1 |  About |  About |      #CAAF |      #CAAF | 
|  1 |  About |  About |  About |      #C6AF |      #C6AF | 
|  1 |  1 |  About |  About |      #CEAF |      #CEAF | 
|  1 |  About |  1 |  About |      #D6AF |      #D6AF | 
|  1 |  1 |  1 |  About |      #DEAF |      #DEAF | 
|  1 |  About |  About |  1 |      #E6AF |      #E6AF | 
|  1 |  1 |  About |  1 |      #EEAF |      #EEAF | 
|  1 |  About |  1 |  1 |      #F6AF |      #F6AF | 
|  1 |  1 |  1 |  1 |      #FEAF |      #FEAF | 
+-----+-----+-----+-----+-----------------+-----------------+ 
                                         
                  -----                  
                                         
    Hdd passport format (512 bytes).     
             All numbers Hex. +-----------+--------+------------------------------------------+ 
| Addr | Length | Meaning | 
+-----------+--------+------------------------------------------+ 
|  LLC |   O2 | Configuration main word | 
|  OO2 |   O2 | Number of cylinders | 
|  OOC |   O2 | Reserved | 
|  OOb |   O2 | Number of heads | 
|  OO8 |   O2 | Number of bytes per track | 
|  OOA |   O2 | Number of bytes in sector | 
|  OOC |   O2 | Number of sectors per track | 
|  OOE |   O6 | Seller Specification | 
|  O14 |   14 | Serial Number (ASCII) | 
|  O28 |   O2 | Controller type | 
|  O2A |   O2 | Cost of the buffer (cache) divided by #2OO bytes| 
|  O2C |   O2 | ECC Code Meaning for Long Rd/Wr Coyands | 
|  O2E |   O8 | Working software version (ASCII) | 
|  O36 |   26 | Model (ASCII) | 
+-----------+--------+------------------------------------------+ 
                                         
   Further, each manufacturer is free to enter
dump anything. Next I have only well-
whether.                                      
                                         
 A word is two bytes,junior/senior.     
 ECC - Egg Control Code.               
                                         
   Due to unclear standards, ASCII
It doesn't look very clear on the passport.
Model stЗ144AT looks like ts1344TA.
This means that if you need to bring this to
screen, you need to swap the first byte
with the second, the third with the fourth, etc. up to
end of line.                            
                                         
      For clarity of terminology:       
                                         
  Drive: My screw:        
80 cylinders 1001 cylinders        
2 heads 15 heads        
16 sectors/track 17 sectors/track  
256 bytes/sector 512 bytes/sector    
                                         
                 -----                  
                                         
Connection diagram for HDD IDE to ZX SPECTRUM. 
                                         
 The scheme is huge in size and typed
in conditional graphics in ordinary text format
doctor, that's why she's not here. But she
It's in the app, so look there.
There are only comments here :( All mikruhi are series 1533.             
                                         
D1 ID7                              
D2 LE1                              
D3 LL1                              
D4 APb                              
D5 TM9                              
D8 LP8                              
D9 LN1                              
D10 LI1                              
D11,12 IR23                             
                                         
   In principle, you don’t have to put D10, it’s
purely buffering, but I wouldn't
Draw directly on the buses of the computer and the screw. D6 and
D7 are responsible for managing 512k memory and
not shown on the diagram. Mikrukhs were calculated
drawn by me from memory with a reference book in hand -
kah.  Diodes - any low-power ones, for example
KDS22.  Unspecified resistor values
are uncritical, selected by eye, in a range
zone 1.5 - 10 k. I printed out the diagram and
I compared it with the original for a long time, glitches like
I didn’t find it. Transistor VT1 is responsible for
blocking hardware reset of the port
#FCAF. You can put any suitable one. 
   You can reset the screw in hardware (bit 6
register #FCAF), or via soft reset in
status control register (bit 2 in
#CAAF).  When resetting, the screw parks the heads and
works out stopping/accelerating the engine, and
it doesn't do him any good.I have
Nya the screw cannot be reset by hardware (reset
bitten on the train), and everything rulesz.
The only way to completely stop
engine - "sleep" command, i.e. "sleep"
so everything is ok.