Inferno #06 03 декабря 2004

Железо

Iron - Description of a block of memory from the printer Robotron CM 6329.01 M. Part 1.

          Description of the memory block

    from the printer Robotron CM 6329.01 M.



   Based on analysis of the scheme include
confirm that the process used in this printer chip UB880D a 
central processor (CPU) Z80. Everything written below applies 
only to this printer model and corresponding block of memory. 
However, used (in the schemes and the printer, and a block) 
Domestic chips show partial or all "our" assembly device, the 
result of which may differ from the original. 


   Further in the text and on the scheme used
 the following notation:

   NC - not connected: This device
this point of the scheme came to nothing connected
(Not used), t.e.signal from this point
going nowhere, and nowhere in it does not arrive at the DIT.

   S0-S7 - the choice: this is my own, simplified notation. 
These signals come from decoder and indicate a choice of one

of 8 units (at any given time assets can be only 1 of 8 
signals), nevybor or all devices (when all the passive system 
driven). 

   P1-P5 - programming: it is my personal
designation. This input voltage programming Upr chip ROM, which 
should give an appropriate voltage, as for programming 
(writing), and at  work (reading).


   CS - chip select: entry of memory chips,
authorizing the work (read / write) with Noah chip data, 
selecting it for access. 

   WE - write permission: Input Circuits
memory, allowing the recording, or
gating the operation of recording information
 which is present on the data bus.

   OE - output resolution: Input Circuits
memory, allowing the output of information from memory on the 
data bus. In the passive state signal on this input data the 
conclusions of memory chips, or work as an input, or are in the 
Z state, t.e.ne load data bus logic signalami.V active signal 
status data findings are outputs and deliver stored information 
to  data bus.


   IEI - enable input interrupt: the signal coming to it, 
allows the formation of the interrupt signal on the basis of 
other hardware and software reasons, otherwise it does not 
(this is my personal suggestion, in the absence of background 
information). This entry is from the port interface CENTRONICS 
and other major chip prints pa. 

   IEO - output interrupt enable: signal is spoken of the 
possibility of interruption under any program and hardware 
events (in the absence reference data is Expected logic). This 
output have some chips, and printer interface CENTRONICS, but

it is not always used. The same-titled light allows the 
formation of limit on closing (the input of the IEI). 

   INT - interrupt: input of the processor
which receives an external signal that indicates any 
sobytie.Protsessor check it before executing the next 
instruction (or at the end of the current instruction 
execution), the main program, and with the active level at this 
input goes to the processing interruption, but only if the 
software is were allowed to (follow the instructions EI).

Just refer to the output device, the classifying formation 
interrupt signal. 

   IORQ - request an external device: output
processor, indicating the work to the outside
device (I / O), as well as confirmation of the interrupt 
(vector interrupt request line). 

   MREQ - Request memory: output processor
indicating that the treatment is
Memory read / write data
or recovery of memory (for dynamic
 RAM).

   RD - read: output processor, indicating that reads 
information from the data bus. In fact, reading is somewhat 
later, because, having received the signal RD, other chips are 
just beginning to give you information on the data bus. 

   WR - write: output processor, indicating that the data bus 
contains information for the record. Can be used as an impulse 
records, because data for this already  present on the bus.


   M1 - machine cycle 1: Output processor
which stands for read data, for immediate implementation (read 
bytes - Operations, rather than the operand). It may also 
denote approval that the interruption of and reading the 
interrupt vector. 

   RES - reset: reset the processor and system
(Printer) as a whole. Processor begins to execute the program 
at address 0, with preemption and dumped registers regeneration 
and interrupt vectors (I, R). [Ed.: This information will need 
to check out! ] The corresponding circuit diagrams when 
resetting can be blocked / razblokirovatsya.S high probability 
we can say that reset occurs only when the printer. While this 
signal is active, the findings address and data are located in 
the Z state and all the control outputs of the processor is not 
the activation vny. 

   CP - Hours: clock frequency, which is a kind of "logical 
power" circuits, the input of the processor and the CLK

to other circuits, synchronizing their joint 
rabotu.Periodicheskoe switching this signal (square wave), 
induce a switch from internal flip-flops, registers and 
counters, chips, leading to the implementation machine 
operations and the system as a whole. 

   BUSRQ - Request tires: the signal coming
this input processor, is often used
for direct access to pamyati.Po this signal, the processor 
completes the current operation and sends its findings to the 
address, data and key control signals in the Z state, to 
capture them on others - triangle buyuschim - device. 

   RFSA - Regeneration: output processor
indicating the presence of at lowest address
Processor numbers next line memory
 for the cycle to restore it.

   A0 - A15 - Address: outputs from the processor,
denoting the number of external devices or
cell pamyati.Takzhe include addresses Chipset
 memory (not all of the A0-A15 in our case).

   D0 - D7 - data: data bus of the processor on which he had 
previously put data to be written and from which it takes

information when chtenii.Dlya memory chips
and port (the main chip printer) bus, on
they give information on reading and
which take the data recording.

   Attention! Signals: S0 - S7, CS, WE, OE,
INT, IORQ, MREQ, RD, WR, M1, RES, BUSRQ and
RFSA - inverted. They are active at logic 0 and logic 1 when 
inactive. Above them taken to draw the line ("underscore 
above), but for technical reasons the data conn text is 
impossible. Just be know that they are active at zero. Signals 
IEO, IEI, presumably, are active in the unit.



   Paper-interface circuit notation: IORQ, INT, IEI, IEO - were 
wrong written by me due to poor quality schemes,

I instead of the letter I wrote to J. I was not sure
the functionality of these signals has not yet
dug into the printer ...


               Appearance.



   Block is made removable module, the board which is placed in 
a plastic black korobochke.Primerno the middle of the board is 
39-pin connector (plug), which block is connected to the main 
board. In this case, all the details of the block, including 
memory chips, are rotated its upside to the main board and 
closed boxes - block body. This eliminates damage to the block 
by external factors, even open the printer. Block

pressed by a special fixing bracket with a screw. Slot on the 
main board for connect the power indicated (on the protective

casing of the mechanical part) as: MEMORY / XB
01.


              Details in general.


   The unit consists of 10 chips and 7 bypass capacitors. An 
electrolytic - subwoofer - capacitor and 4 nonpolar - "high" - 
posted next to the ROM, two more non-polar capacitors are 
placed in RAM and decoder. The scheme figures shows the 
locations of circuits, if you look at the detached block of 
memory, and a conditional position connector pins, which I took 
myself, it may be different from the present. Also dots and 
dashes shows the capacitor, and a rectangle - the connector. 



                   Rom.



   5 ROM chip soldered without sockets -
a domestic chip KM573RF2 volume
only 2 kilobytes each. Designation ROM
taken from reference data, and fully corresponds to the truth 
(about the original designation of five chips with read below). 
To read the information on the OE input of all these chip 
receives a signal processor RD. To select a particular chip on 
her receives the appropriate signal S0 - S4.

Conclusions Upr all circuits (signals P1-P5)
connected to the individual connector contacts
and work on all these contacts come
Voltage - +5 V required to
normal operation (read data).


                   RAM.



   4 chips, which form of RAM, import:
U214D30. Without a shred of information about
them, I can only assume (based on
preparing the plan for unit and signals from the main board), 
which is a static memory Simplified dostupa.Oboznachenie RAM 
was himself, and it may differ from the present (eg, numbered 
addresses and data that does not affect the logic of the memory

because the total number of addresses (and, consequently, 
memory cells) consistently as and the number of bits). In 
particular, it may be different names of the control signals - 
CS and WE, although this is unlikely. Presence

only two signals, said on a simplified management. Low signal
CS, coming from the decoder (signal S6
or S7) when addressing the RAM permits operation with memory - 
selects the memory access. A low level WE signal writes the 
data to pamyat.Est only one thing: high level WE signal 
indicates reading of memory t.e.etot input controls the 
direction of data transfer, but records low WE comes in last

turn (at WE signal processor WR Z80), when the data bus is 
already information for writing into the memory. But up

before entering the recording signal (WE = 0) itself
Memory gives information - works in read mode. Therefore, when 
writing data to the RAM for a few cycles of CPU time the data 
bus is loaded with two sources: on the one hand, memory

issued the old information with the other -
processor, have prepared a new informatsiyu.Prichem processor 
must win, otherwise written invalid informatsiya.Eto indicates 
the specificity of the RAM, it should have limited output 
current - a complex scheme of output, and dissipate the energy 
loss for the closure of the data bus. Perhaps therefore, 4-bit 
memory, and each chip in volume only one kiloTetradu. However, 
there is another option - split addressing reading and writing. 
We can assume that one of the lowest address (A0-A9), 
permanently connected to the RAM, does not come on address 
input and the input of the OE, and thus controls the output 
data from RAM. Then on one of the addresses of memory access 
(when This address = 0), RAM provides information and on

others (where the address = 1) RAM do not
issues, but is available for recording data. When
This conflict on the data bus (with two signal sources) does 
not arise, because in firmware provides separate access to

memory for her writing and reading. But since 1
memory address in this case is the input
OE, the amount of memory for each chip twice
smaller and is only 0.5 kiloTetrady,
and the total amount of RAM - only 1 kilobyte.

   This - conflict-free - option scheme
more plausible, and a control address,
most likely, senior - A9, because then the memory "breaks" into 
two halves: the first for reading and one for writing - simply 
nowhere (if you use a different memory addresses will be split 
into several parts, one half will be for the record, and half 
others to read - not too convenient mnogokusochnaya 
addressing). Thus, conflict-free version of the memory address 
at administered address A9, 15 foot RAM is not really A9, and 
the input OE. But contrary to for this is that the printer (as 
in passport) supports graphics mode with 1920 points in line. 
And for that just need about 2 kBytes OZU.Hotya quite logical 
that in graphics mode flash provides (in need to) print out in 
two stages - for first and second half of the line separately,

respectively, requires half the memory. In general, the 
addressing of RAM (no exact reference data) in question: one of

two.


               Decoder.


   Chip decoder chip integrates
ROM and RAM in a shared address space
processor, allowing access to memory, based on a combination of 
signals to access it. Since I have no information about the 
chip UCY74S405, it can only expect (based on compiled

circuits and signal processor) that is deshifrator.Na scheme 
does not fit, and I just listed all suitable to his feet 
signals (with feet 1 foot to 16). With great probability we can 
say that an indirect analog simple decoder

"3 8" (our label: ID7), because
logic of his actions in relation to this
scheme as the pinout is identical.
In this case, the decoder decodes 3
bits of the address A11-A13 (except junior
A0-A10, directly connected) and provides selection signals to 
the memory chip (S0-S7). But he does it, if the processor is 
located in lowest address (the signal A14 = 0), works with

Memory (alarm MREQ = 0) and reset (or
discharge has already passed, the signal RES = 1). Iterating 
combinations Senior (A11-A13) addresses, signals S0-S7 series 
switch Products pamyati.V up memory addressing

following: first, there are 10 kilobytes
ROM (chip D1-D5), then 2 kilobytes
memory available (because the S5 is not used
and is designated as NC), followed by 4 kilobytes of RAM (each 
kilobyte of RAM is duplicated, repeats of the address twice; 
because signal A10 in the sample RAM is not used in the 
conflict-free version of the RAM contains the first 512 bytes 
to read, then they are repeated for the record, then the first 
512 bytes duplicated (for reading and writing), then

similarly has the second 512 bytes
RAM), then 16 kilobytes of memory available
(Signal A14 = 1, and prohibits the selection of memory)
and, finally, 32 kilobytes of repeating the previous layout (as 
the senior address CPU - A15, in the sample memory of the

unit is not involved). As a result, we get 64
kilobytes of memory to the processor Z80.


    The combined notation mokroshem.


   The diagram shows two chips, while
in fact their 10. Decoder does not fit, but the signals on its 
conclusions are listed, which is sufficient for understanding 
the logic of work. The remaining 9 chips depicted as two sets 
of combined chips. Such is the "logical method" is often

using a simplified scheme of memory blocks. This saves space in 
the scheme, and even makes its readership, accelerates 
understanding, not Considering the first moments of 
familiarization with shemoy.Osnovnoe usually read these schemes:

legs, which are not repeated - belong
(Connected in parallel) all combined the chips (and they are 
fed the same signal); feet, which includes several time, belong 
to different circuits of the association, and they come to 
different, not interconnected signals. Under feet have in mind 
the conclusions of chips, whose numbers are present one or more 
times one marking scheme. On the contrary, "reusable" legs in 
the notation is the number chip (one or several) to 
sootvetstvuyuschimu conclusion which (who) comes this signal 
(s). It is easy to see that all ROM chips almost zaparalelleny 
separately on each signal comes only choice and programming 
voltage. A chip RAM are connected trickier. Because each chip

there are only 4 bits of data for
bytes need to enable access immediately to 2
chips (one minor issue, and other high-order bits of data), 
input selection are connected in parallel, and the findings of 
the data are separately but zaparaleleny with the findings of 
these other 2 chip RAM, which is also connected in parallel 
inputs of the sample, the remaining inputs of all chips of RAM 
in parallel. Capacity is indicated for one (each) chips in the 
set, and for main memory can be halved.



             Others on the scheme.

   Signals feeding simplified notation
both plus and minus, minus corresponds to GND,
GND printer, plus - +5 V, power supply ICs printer.

   Directly next to the pin chips specified designation signals 
connected to them (the same name signals in the scheme, by 
itself, connected), the following notation - the coordinate of 
the contact in the plug. May seem that the 39-pin connector is 
used by half, but in reality, only 5 remain unconnected 
contacts - they are listed in a vertical window in the middle, 
in the end all contacts listed plug. 

   Signals with the same name - are the signals of the 
processor, and when installing the unit connected to it. 

   When listing the legs decoder D10
first the name of the signal at
this leg, the second coordinate signal
connector (if it is connected to it). The first
three legs decoder (on the alleged
analogy with our ID7) are input
bits, the next three - permits the signals of choice (the first 
two of which are inverted - are active at 0), others (not 
counting supply) are the outputs decryption of input bits.


   Indicated capacitors (C1 - C7 - numbering convention!).

   In addition to the name of the scheme, its alternate name 
and date specified abbreviation BGE - used for drawing graphics 
editor. Also there is a discharge logo "FREE CAT". 


        Prospects and modification.


   This block of memory is the total
memory module include both RAM and
ROM (which also shows the notation in
printer). Since the unit is removable, for sure
There are many modifications to it, and
should determine the designation of the unit.

   On the reverse side of the board memory is marking the date 
of manufacture (or firmware): May 26, 1988 (very bad

seen could be wrong). On the circuit side of the board etched 
Technology Room: 05-260-6111-0B0a (probably has to do with

to software or its specification). With the plug stuck a small 
print (perhaps it is the printer): 3.38-3-08/04; line below: 
V24/CL/IFSP EPS; last Line: US ASCII / KYR 0. This is the last,

information says about a particular version
firmware, possible priority interface
EPSON standard encoding version of the table of ASCII 
characters and Cyrillic. 5 unused (in block) contacts the plug 
in most printers are connected, and they account for the 
following signals: B5 M1, B6 A15 (in This printer is cut track 
and jumper, and actually come here signal RFSA), B9 BUSRQ, B13 
GND, C9 CP. We can say that the printer is designed to

connection of different blocks of memory with
using both dynamic and static memory of the different sizes, up 
to 32 kilobytes. In general, when the presence of such signals 
can even expand addressable memory processors. Previously, 
static RAM were rare, and had a small volume

(Take the 4 chips - total capacity of not more than 2 
kilobytes), the dynamic was more common and is much more to 
emkostyu.Poetomu connector provides signal regeneration

heap, although this printer
instead connected to A15, which allows
use every opportunity to Z80 64 kilobytes of memory, but static.

   Modern block of memory for this printer, with 32 kilobytes 
of ROM and 32 kilobytes of RAM, may consist of only 5 items 
(Excluding connectors): low frequency, high frequency 
capacitor, the actual ROM RAM and decoder.


   As for this block of memory, the only possibility 
Effectiveness its use - is to build the programming for him. 
Because memory chips are soldered, remove them (for 
doproshivki) is problematic. Even if you do it, using 
information another block, the tracks may come off

(For desoldering ROM and install the sockets for
them), and the reliability of the result will be low. 
Therefore, the assembly programmer (in the simplest form is 
just a interfeysperehodnik, with the appropriate plug adapter 
electronic key for switching voltage programming) - the most 
reliable option. 

   Unfortunately, this printer does not provide for the 
possibility of flash memory blocks. The fact that the contacts 
to which a memory unit suitable voltage output

programming in the printer enters the supply voltage +5 V. It 
comes directly, and no possibility of switching it is not 
(there are no jumpers or fuse, which could break

this circuit to feed her pulse of programming - 25 V). Even if 
we cut track (which is connected by a connector, and I have no 
idea how to do it) and collect key programming voltage,

then there must be the firmware,
supporting it - we get a closed
circle.

   Given the operation of the printer
1990, since the latest firmware for
Today there was a minimum of 14 years. Time
data storage chips 573 Series
P ^ 2 is 100 thousand hours off as a (power is four times 
smaller, but since the printer almost did not work, we can not 
consider), ie 12 let.S account dual-supply reliability can be 
said Over the next 12 years (at least 2 years

which have already passed) the information in the ROM is 
uniquely undergo changes, and correct the printer can no longer 
count on. 

   Obviously once (when going to these
printers), there was a programmer in which to insert the block, 
and all of a ROM for another pierced. Given the popularity of

these printers at one time, one can assume that in the 
warehouses of different industrial organizations could 
collapsing similar programmer, but the computer with which he

was connected, probably did not survive this time
(Due to the erasure of their firmware - maybe even so). But the 
presence of the programmer might help him to adapt to another 
system. 



   The next part of this text file
will eventually be disconnected, and after a little revision, 
both file and block diagram memory will be placed in the 
archive (named  type of RBT).