Hardware - IDE controller.

 Hello editors of ADVENTURER magazine!             
                                                                
   Vladislav writes to you from Cherkassy. Thank you very much for the magazine.
The reason for this letter was the second version I developed
IDE-HDD adapter circuits which became part of the peripheral
controller. This article is based on the previous one, and is
updated and supplemented material, which takes into account
features of the second version of the scheme. I didn't do it in the article
links to the previous one, for the reasons that not everyone can
turn out to be Adventurer #13 and the opportunity to purchase it.        
   I am currently developing software support and hardware alone. What
concerns iron, then I personally assembled it in
keyboard case from "Robik" Spectrum: 2Mb RAM; 32K ROM;
FDD HD/DD Turbo controller; IDE-HDD adapter v2. 0; MC146818A;
AY8910; Giga-screen; LPT port;i8042;FDD 3. 5`;HDD Seagate 85OMb;
15OBt power supply.  I started assembling a sound card with direct
access. If you have any information on it or
software support, my E-mail: vmatlash@icu.net              
                                                                
   I hope that the new scheme will be useful to the reader. In advance
grateful.Mail:                                                          
Ukraine,                                                        
18002 Cherkasy                                               
st. Lenina 10, apt. 6                                            
Matlash Vladislav                                              
----------------------------------------------------------------
              Second version of the IDE-HDD adapter circuit              
                                                                
   Distinctive features of the scheme:                             
   1. High repeatability                                     
   2. Available element base                                 
   3. Simplicity, accessibility of assembly and adjustment even for a beginner   
   4. Quick adaptation of drivers for other similar adapters
from (C) Nemo, (C) Slot & Co...                                  
   5. Full support for block input/output commands (INI,
INIR, OUTI, OTIR) speeding up data transfer, which saves
memory and time                                                  
   6. Work in both short and long addressing           
                                                                
                                                                























                                                                
                                                                
           Переченьelements                                   
+-------------------------------------+                         
|              MICROCIRCUITS |                         
+---------+-----------------------+---+                         
| DD1,DDЗ | KP1533UP22 (7ХALSЗ73) | 2 |                         
| DD2,DDS | KP1533UP23 (7ХALSЗ74) | 2 |                         
| DD7 | KP15ZZAPb (7ХALS245) | 1 |                         
| DDCH | KP15ZZLI1 (7ХALSO8) | 1 |                         
| DDb,DD8 | KP15ZZID7 (7ХALS138) | 2 |                         
| DD9 | KP15ZZID14 (7ХALS139) | 1 |                         
+---------+-----------------------+---+                         
|             CAPACITORS |                         
+---------+-----------------------+---+                         
| C1 - C9 |  0.68 - 0.1 µF | 9 |                         
| C10 |  20 µF x 6.3 V | 1 |                         
+---------+-----------------------+---+                         
|              RESISTORS |                         
+---------+-----------------------+---+                         
| R1,R2 |       10K | 2 |                         
| R3 |      300 Ohm | 1 |                         
+---------+-----------------------+---+                         
|               CONNECTORS|                         
+---------+-----------------------+---+                         
| X1 | SNPS8-64/94x9V-23-1-V | 1 |                         
| X2 | ONP-KG-56-40-B53 | 1 |                         
+---------+-----------------------+---+                         
                                                                
                                                                
 The principle of operation of the circuit                      
                                                                
   This scheme allows you to connect up to two drives per
hard magnetic disks (HDD) of almost any capacity, and
as well as other devices designed for the ATA (IDE) interface.     
                                                                
   The scheme consists of six main parts:                      
                                                                
   1. Decoder of input-output ports of the IDE device,
made on DDb (ID7) and DD8 (ID7) microcircuits.              
   2. Short or wide operating mode control circuit
addressing.                                                      
   3. Data bus word generation block [D15:D0] for recording
into a device made on 8-bit registers DD1 (IR22) and
DD2 (IR23).4. DDS register (IP23) for latching the high byte of the word
data bus [D15:D8] of the device during reading.                
   5. Bidirectional 8-bit buffer DD7 (APb) for
forming the low byte of the data bus word [D7: D0].         
   6. Register DDCh (IR22) for buffering control signals
device DAO, DA1, DA2, DIOW#, DIOR#, RES#.                  
                                                                
   The decoder DD8 (ID7) generates a signal (AE#) log. 0 output
[9] allowing the operation of decoders DD9 (ID14) and DDb (ID7),
which generate control signals for the operation of the circuit:            
   - RWE# - low logical level enables registers DD1
(Р22) and DD2 (Р23) set the word [D15:D0] to the data bus
device, generates a signal at the output of element 2-I DDCh.1 (LI1)
(SCE) logical zero, which is combined with the signal (A3) on
decoder DD9 (ID14) will generate signals accordingly
(CASO#) and (CAS1#) to select a block of device registers.        
   - WWC# - on the edge of this signal a byte will be written from the bus
computer data into the 8-bit register DD2 (IR23) for
forming the low byte of the word [D7:D0] on the data bus
devices.                                                     
   - RWC# - low logical levelgenerates at the output
element 2-AND DDCH.2 (LI1) signal (WRE#) logical 0,
allowing bidirectional 8-bit buffer DD7 (APb)
open the channel.  The direction of transmission is indicated by the signal (RD#)
data to pin [1] DD7 (APb), with this level active
signal low byte of the word [D7:D0] from the device data bus
will be transferred to the computer data bus.                        
   The edge of the signal (RWC#) will latch the high byte of the word [D15:D8] with
device data bus in the DDS register (IP23) for the possibility
read by the processor.                                         
   - LHE# - generated during short decryption and similar
signal (RWC#), only the front of the signal has no influence.
                                                                
                                                                
            Brief instructions for assembly and configuration            
                                                                
   With proper assembly and serviceable components, setup
no adapter is required, but if you are unlucky and purchased
the element base leaves much to be desired, I advise you to read
this instruction.                                              
   To identify faults and verify correct assembly
The following measuring equipment is needed:- voltmeter or tester (multimeter);                         
   - logic probe (in case you don’t have an oscilloscope). 
                                                                
   Before you configure the adapter, you must configure it
assembly.                                                         
   To do this you will need a double-sided foil
fiberglass 70x90 mm in size.  On both sides of which
scratch the power bus and places for soldering under the line
microcircuits and connectors SNPS8-64/94x9V and ONP-KG-56-40-B53 according to
(Fig. 2).                                                       
                                                                
   To scratch foil, I use a cutter made from
a blade from a metal saw that has served its useful life, cutting it off
to the desired length and putting one of the sides on a grinding wheel
view of a sharpened “claw” (see Fig. 1).                           
  
  
  
  
  
  
  
  
  
                                                                
   To reduce the search for faults, check the absence
short circuits and breaks of conductors on the board using a tester.
Install microcircuits, connectors and solder them. At the same time I recommend
use a soldering iron with grounding and flux (glycerin +
chloramonium with a ratio of 95% to 5%). Before soldering the chips
It is advisable to tin the board with POS-62 solder to avoid
unwanted oxidation of copper foil.  To reserved
The area of side "A" of the board is to supply the ground potential (GND).         
   Installation of conductors is carried out using MGTF-0.03 wire according to the diagram.
To fix which on the board you should use guides
rings of copper wire with a diameter of 0.5 mm soldered
perpendicular to the power bus.   For each chip
It is recommended to install a 0.1 µF blocking capacitor according to
power supply to eliminate parasitic interference.  To the power bus
It is advisable to install an electrolytic capacitor with a capacity of 20
µF x 6.3 V.


















                                                                
                           Сторона А                            




















                                                                
   После проверки тестером правильности монтажа проводников и на
отсутствие замыканий выводов микросхем, плату промывают от флюса
под  проточной  горячей водой (если не пользовались канифолью) и
дают ей высохнуть.                                              
   Следует  отметить,  то,  что обрыв и замыкания сигналов могут
быть  не  только  между проводниками платы, а еще и внутри самих
микросхем.Next, to connect the adapter, do the following:
actions:                                                       
   1. Insert the adapter into a free interface connector
computer.                                                     
   2. Connect the 40-pin connector of the IDE drive cable. The most
common errors in connecting cables are
turning the connector 180 degrees and lateral or longitudinal
contact displacement. A plastic rim saves you from these mistakes,
surrounding the pins of the highest quality connectors, and its
key slot. However, there are also embarrassments with keys: it happens
that the connector of the cable, having a corresponding key protrusion, to the cable
pinned incorrectly.  Then for the correct connection this
the protrusion has to be cut off (this is easier than cutting it properly
connector).  I personally encountered this problem when connecting the IDE
cable to the hard drive.                                             
   3. Connect the hard disk access indicator "HDDLED" to
two-pin connector on the adapter board. Connect correctly
connector is possible while booting from the hard drive - in this case
the indicator should flash.To quickly check that the entire connection is correct, type:
10 PRINT AT 0.0;IN 199;" ":GO TO 10                            
                                                                
   If everything is correct, then after passing the internal test
the device should flash the number 80 on the screen.                  
                                                                
   This setup description is very brief due to
inability to reflect all kinds of faults and options
adapter assembly.   It serves as a build and run algorithm
limited to just a few tips.                         
                                                                
                                                                
                     Software control                     
                                                                
   For programmatic interaction with connected devices
to the adapter, in the computer I/O space was selected
port address area (see Fig. 3).                            
















 Fig. 3. Organization of the port for selecting IDE device registers     
                                                                
   The adapter I/O port space is selected as follows:
so that you can use automatic commands
input/output MP Z80 and access the device registers by
short decryption without participation of the high part of the address bus
[A15:A8].                                                       
   The advantage of this is that the number of cycles is reduced
processor (and therefore time) spent on
operations of data exchange with the device and saves memory for
driver programs.   Usagesemi-automatic commands
I/O revealing the exchange cycle will significantly increase
speed.                                                       
   This distribution of port space does not exclude
possibility of conflicts with other devices that do not scan
all addresses [A0:A7]. To eliminate this shortcoming, organize
ability to enable/disable the adapter with a free bit
system port by supplying the corresponding output to the pre-
decoder pin [5] or [4] disconnected from the "GND" potential
DD8 (ID7).                                                      
                                                                
           Address space of I/O ports            
                                                                
                    Table 1. I/O address space
+-+-+-+-----+-----+--+--+------------------+-------------------+
|A|A|A|A A A|Port |CS|CS|Read | Write |
|8|4|3|2 1 0|hex |0#|1#|                  |                   |
+=+=+=+=====+=====+==+==+====+====+
|x|0|0|0 0 0|xxC0 |0 |1 |(DR) D[7:0]|(DR) D[7:0]|
|х|0|0|0 0 1|xxC1 |0 |1 |(ER) |(ER) |
|x|0|0|0 1 0|xxC2 |0 |1 |(SC) |(SC) |
|x|0|0|0 1 1|xxC3 |0 |1 |(SN) LBA[7:0]|(SN) LBA[7:0] |
|x|0|0|1 0 0|xxC4 |0 |1 |(CL) LBA[15:8] |(CL) LBA[15:8] |
|x|0|0|1 0 1|xxC5 |0 |1 |(CH) LBA[23:16] |(CH) LBA[23:16] |
|х|0|0|1 1 0|xxC6 |0 |1 |(D/Н) LBA[27:24] |(D/Н) LBA[27:24] |
|x|0|0|1 1 1|xxC7 |0 |1 |(SR) |(CR) |
+-+-+-+-----+-----+--+--+------------------+-------------------+
|x|0|1|0 x x|xxC8-|1 |0 |Not used.  [7:0]|Not used.  D[7:0]|
|x|0|1|1 0 x|-xxCD|1 |0 |Not used.       |Not used        |
|x|0|1|1 1 0|xxCE |1 |0 |(AS) |(DC) |
|x|0|1|1 1 1|xxCF |1 |0 |Not used.       |Not used        |
+-+-+-+-----+-----+--+--+------------------+-------------------+
|0|1|0|0 0 0|xnC0 |0 |1 |(DR) D[7:0]|(DR) * D[7:0]|
|0|1|0|0 0 1|xnC1 |0 |1 |(ER) |(DR) * |
|0|1|0|0 1 0|xnC2 |0 |1 |(SC) |(DR) * |
|0|1|0|0 1 1|xnC3 |0 |1 |(SN) LBA[7:0] |(DR) * |
|0|1|0|1 0 0|xnC4 |0 |1 |(CL) LBA[15:8] |(DR) * |
|0|1|0|1 0 1|xnC5 |0 |1 |(CH) LBA[23:16] |(DR) * |
|0|1|0|1 1 0|xnC6 |0 |1 |(D/Н) LBA[27:24] |(DR) * |
|0|1|0|1 1 1|xnC7 |0 |1 |(SR) |(DR) * |
+-+-+-+-----+-----+--+--+------------------+-------------------+
|1|1|0|0 0 0|xnD0 |0 |1 |(DR) * D[15:8]|(DR) D[15:8]|
|1|1|0|0 0 1|xnD1 |0 |1 |(DR) * |(DR)|
|1|1|0|0 1 0|xnD2 |0 |1 |(DR) * |(DR) |
|1|1|0|0 1 1|xnD3 |0 |1 |(DR) * |(DR) |
|1|1|0|1 0 0|xnD4 |0 |1 |(DR) * |(DR) |
|1|1|0|1 0 1|xnD5 |0 |1 |(DR) * |(DR) |
|1|1|0|1 1 0|xnD6 |0 |1 |(DR) * |(DR) |
|1|1|0|1 1 1|xnD7 |0 |1 |(DR) * |(DR) |
+-+-+-+-----+-----+--+--+------------------+-------------------+
|0|1|1|0 x x|xnD8-|1 |0 |Not used.  [7:0]|Not used.  D[7:0]|
|0|1|1|1 0 x|-xnDD|1 |0 |Not used.       |Not used        |
|0|1|1|1 1 0|xnDE |1 |0 |(AS) |(DC) * |
|0|1|1|1 1 1|xnDF |1 |0 |Not used.       |Not used        |
+-+-+-+-----+-----+--+--+------------------+-------------------+
|1|1|1|0 x x|xnD8-|1 |0 |Not used. [15:8]|Not used. D[15:8]|
|1|1|1|1 0 x|-xnDD|1 |0 |Not used.       |Not used        |
|1|1|1|1 1 0|xnDE |1 |0 |(AS) * |(DC) |
|1|1|1|1 1 1|xnDF |1 |0 |Not used.       |Not used        |
+-+-+-+-----+-----+--+--+------------------+-------------------+
*: latch register, x: any value, n: only A8 has a value 
                                                                
Alternate Status (AS) - alternative status register        
Device Control (DC) - device control register          
Data (DR)- data register                          
Eggrog (ER) - error register                          
Features (FR) - property register                         
Sector Count (SC) - sector counter register               
Sector Number (SN) - sector number register                  
Cylinder Low (CL) - register of the low byte of the cylinder number  
Cylinder High (CH) - register of the high byte of the cylinder number  
Device/Head (D/Н) - device and head number register     
Status (SR) - status register                       
Command (CR) - command register                          
                                                                
                                                                
;Example of a subroutine for reading a device identification sector    
        ORG #C000                                               
INSTL DI                                                      
L2 IN A,(#C7) ;Status register                       
        CP #50                                                  
        JR Z,L1 ;No errors                             
        CALL #1F54 ;Checking whether BREAK is pressed                 
        RET NC                                                  
        JR L2                                                   
L1 LD C,#C7L3 IN A,(C)                                                
        RLCA                                                    
 JR C,L3 ;Waiting for the device to be ready             
        LD A,#EC ;Command                                
        OUT (C),A ;Command register                         
L5 IN A,(C)                                                
        BIT 7.A                                                 
        JR Z,L4 ;We accept a package of 256 words               
        CALL #1F54                                              
        RET NC                                                  
        JR L5 ;Waiting for response                             
L4 LD BC,#00D0 ;Data register                          
        LD HL,50000 ;Receipt address                
        INIR                                                    
        INIR                                                    
        RET ;Successful exit                         
                                                                
Fragment of reading a data sector No. of Z80 cycles No. of bytes    
. . .                                                           
LD HL, buffer address 10 3            
LD BC,#00D0; Port address 103            
INIR (INI 256 commands) 21/16 2            
INIR (INI 256 commands) 21/16 2            
. . .                            ----- ---            
Total: 10762 10            
When the loop is open: 8212 518            
                                                                
Fragment of data sector recording No. of Z80 cycles No. of bytes    
. . .                                                           
LD HL, buffer address 10 3            
LD BC,#00D0; Port address 10 3            
OTIR (OUTI 256 commands) 21/16 2            
OTIR (OUTI 256 commands) 21/16 2            
. . .                            ----- --            
Total: 10762 10            
With the cycle open: 8212 518            
                                                                
                                                                
                     ATA Device Registers                     
                                                                
   Each ATA device has a standard set of registers,
addressed by signals from the host adapter (CSO#,CS1#, DA2, DA1,
DAO, DIOR# and DIOW#). The set of registers (Table 2) consists of two
blocks selected by CSO# or CS1# signals.  Command block
registers are used to send commands to the device and transmit
information about his condition.   Control register block
used to control the device and receive its bytes
condition.  The validity of the contents of the command registers
block and alternative status register indicates zero
the value of the BSY bit of the status register.   If the device
Supports power management, sleep mode
Sleep mode the contents of these registers are invalid.           
                                                                
                  Table 2. Registers of ATA device controllers
+---------------------+---------------------------------------+
|        Address |                                        |
+----+----+---+---+---+Purpose (R - read, W - write) |
|CSO#|CS1#|DA2|DA1|DAO|                                        |
+====+====+===+===+===+=========================================+
|1 |1 |x |x |x |Not used (data bus in third |
|    |    |   |   |   |condition) |
+----+----+---+---+---+----------------------------------------+
|Control block registers - block of control registers|
+----+----+---+---+---+----------------------------------------+
|1 |0 |0 |x |x |Not used (data bus in third |
|    |    |   |   |   |condition) |
+----+----+---+---+---+----------------------------------------+
|1 |0 |1 |0 |x |Not used (data bus in third |
|    |    |   |   |   |condition) |
+----+----+---+---+---+----------------------------------------+
|1 |0 |1 |1 |0 |R: Alternative Status (AS) - alter-|
|    |    |   |   |   |active status register |
|    |    |   |   |   |W: Device Control (DC) - control register-|
|    |    |   |   |   | using the device |
+----+----+---+---+---+----------------------------------------+
|1 |0 |1 |1 |1 |Not used * |
+----+----+---+---+---+----------------------------------------+
|Command block registers - block of command registers |
+----+----+---+---+---+----------------------------------------+
|0 |1 |0 |0 |0 |R/W: Data (DR) - data register |
+----+----+---+---+---+----------------------------------------+
|0 |1 |0 |0 |1 |R: Eggrog (ER) - error register |
|    |    |   |   |   |W: Features (FR) - property register |
+----+----+---+---+---+----------------------------------------+|0 |1 |0 |1 |0 |R/W: Sector Count (SC) - register counters-|
|    |    |   |   |   |ka sectors |
+----+----+---+---+---+----------------------------------------+
|0 |1 |0 |1 |1 |R/W: Sector Number (SN) - number register|
|    |    |   |   |   |sectors |
|    |    |   |   |   |LBA[7:0] ** |
+----+----+---+---+---+----------------------------------------+
|0 |1 |1 |0 |0 |R/W: Cylinder Low (CL) - register lower-|
|    |    |   |   |   |th byte of cylinder number |
|    |    |   |   |   |LBA[15:8] ** |
+----+----+---+---+---+----------------------------------------+
|0 |1 |1 |0 |1 |R/W: Cylinder High (CH) - register old-|
|    |    |   |   |   |low byte of cylinder number |
|    |    |   |   |   |LBA[23:16] ** |
+----+----+---+---+---+----------------------------------------+
|0 |1 |1 |1 |0 |R/W: Device/Head (D/Н) - number register|
|    |    |   |   |   |devices and heads |
|    |    |   |   |   |LBA[27:24] ** |
+----+----+---+---+---+----------------------------------------+
|0 |1 |1 |1 |1 |R: Status (SR) - status register |
|    |    |   |   |   |W: Command (CR) - command register |+----+----+---+---+---+----------------------------------------+
|0 |0 |x |x |x |Invalid address |
+----+----+---+---+---+----------------------------------------+
   * The register falls out of the block.                               
  ** The sector, cylinder and head register in LBA mode contain
     specified logical address bits.                         
                                                                
   THE STATUS REGISTER reflects the current state of the device in
the process of executing commands. Reading the status register allows
further changing its bits and resetting the interrupt request.    
   Bit 7 - BSY (Busy) indicates the device is busy. With him
single value, the device ignores attempts to write to
command block of registers, and reading these registers gives
undefined result (their device value may be
changed at any time).  When this bit is set to zero
command block registers are accessible and the device can change
only the value of the IDX, DRDY, DF, DSC and CORR bits.  Bit
installed under the influence of hardware and software reset
device, as well as upon receipt of a command.   Bit can
be installed for a short-term interval, so that the host
may not notice this fact.                                
   Bit6 - DRDY (Device Ready) indicates readiness
devices to perceive any command codes. If the bit state
changed, it cannot change back before reading the register
condition.  When the bit value is zero, the device perceives
EXECUTE DEVICE DIAGNOSTIC and INITIALIZE DEVICE commands only
PARAMETERS, stopping execution of the current command and reporting
this flag ABRT in the error register and ERR in the status register.
Receiving other commands when the DRDY bit is zero results in
unpredictable results.                                    
   Bit 5 - DF (Device Fault) - device failure indicator.     
   Bit 4 - DSC (Device Seek Complete) - completion indicator
track search.                                                   
   Bit 3 - DRQ (Data Request) - indicator of readiness for exchange
word or byte of data.                                       
 Bit 2 - CORR (Corrected Data) - indicator of corrected error
data.                                                         
   Bit 1 - IDX (Index) - index, interpreted specifically for
each manufacturer.                                          
   Bit 0 - ERR (Eggrog) - indicator of the previous execution error
operations.                                                       
   Additional information is contained in the error register. If
bit setERR, until the next command is received, software
or a hard reset will not change the state of this
bit, as well as an error register, a register for the number of sectors and
cylinder registers, head registers and sector numbers.                   
   ALTERNATIVE STATUS REGISTER has the same bits as
basic, but reading it does not lead to any changes
device status.                                           
   The purpose of the COMMAND REGISTER is obvious from the name. Device
starts executing the command as soon as its code is
written to this register.                                       
   REGISTERS CYLINDER NUMBER (high and low bytes) and NUMBERS
SECTORS have a dual purpose depending on the chosen
addressing systems (CHS or LBA).   They are initialized
host adapter, and if an error occurs during the operation
the device will place in them the address at which the error was encountered.
   DEVICE AND HEAD NUMBER REGISTER except for part storage
address information is used to select device-0 or
device-1 and addressing method. Bits 7 and 5 are reserved.    
   Bit 6 - L - a single value indicates the use
LBA addressing mode.  When the bit is set to zero, the
CHS mode.                                                      
   Bit 4 - DEV (Device)- device selection. When DEV=0 selected
device-0 (Master), with DEV=1 - device-1 (Slave).        
   The [3:0] bits have a dual purpose depending on
selected addressing system.  In CHS mode they contain the number
heads, in LBA mode - the most significant bits of the logical address. Like
previous, this address register is initialized
host adapter, and if an error occurs during the operation
the device will place in them the address at which the error was encountered.
   Before the adoption of the ATA-2 standard, it was believed that address registers
must be modified after the operation has been successfully completed,
reflecting the current value of the address in the media.                     
   DATA REGISTER can be used as 8-bit or
16-bit depending on the type of data transferred in the current
team.                                                        
   Only two of the DEVICE CONTROL REGISTER are used
bits, bits [7:3] are reserved, bit 0 must always be
zero.                                                        
   Bit 2 - SRST (Software Reset) - software reset, active
all the time until the bit is reset.  Both bus devices
perceive a soft reset at the same time.                    
   Bit 1 - IEN# (Interrupt Enable) - inverse enable bit
interruptions. At zero valuebit the selected device can
generate the INTRQ signal via a tristable output.            
   ERROR REGISTER stores the execution status of the last operation
or diagnostic code.  After completing the operation, check for availability
the error detected by this register is indicated by the ERR bit
status register.                                             
   Bit 7 is reserved.                                        
   Bit 6 - UNC (Uncorrectable Data Ergo) - unrecoverable error
data.                                                         
   Bit 5 - MC (Media Changed) - media change. After the shift
carrier, the first call command is rejected and
This error bit is set.  After resetting this bit
the following commands will run normally.         
   Bit 4 - IDNF (ID Not Found) - indicates not found
sector identifier.                                          
   Bit 3 - ABRT (Aborted Command) - set if
the command is rejected as invalid or in case
another error occurs.                                      
   Bit 2 - MCR (Media Change Requested) - request indicator
change media.   After detecting a media change request
subsequent DOOR LOCK commands will return the ERR error bit and
MCR bit set.  MCR bitreset by DOOR commands
UNLOCK, MEDIA EJECT or hard reset.                     
   Bit 1 - TKONF (Track 0 Not Found) - indicates that
The RECALIBRATE command was unable to find the null track.              
   Bit 0 - AMNF (Address Mark Not Found) - address not found
data marker in the sector header.                              
   After turning on the power, performing a reset or command
EXECUTE DEVICE DIAGNOSTIC error register contains
diagnostic code.                                            
   PROPERTIES REGISTER (a more appropriate equivalent to the name
Features Register could not be found) used depending
from the team.  In the SET FEATURES command, for example, it allows
manage caching. Some devices may ignore
entry to this register. In a number of systems developed before the adoption
standard ATA-2, the value of the recommended value was placed in this register
cylinder numbers for write precompensation.                     
   SECTOR COUNTER REGISTER contains the number of sectors
participating in the exchange. The host initializes this register before serving
commands (zero value corresponds to 256 sectors).  By
successful completion of a data access operation, the register must
reset. If the command fails, the register will show
number of sectors that must be transferred for successfulcompletion of the previous request.  Some commands (INITIALIZE
DEVICE PARAMETERS or WRITE SAME) may override the value
this register.                                                 
                                                                
                         Command system                         
                                                                
   The ATA-2 standard also specifies the COMMAND SYSTEM, which is given in
table 3. In this table, the column <> defines the method
transmission of data required for the command: PI - data input from
devices in PIO mode, PO - data output in PIO mode, DM -
data exchange via DMA channel, ND - no data exchange, VS -
device specific.    Column <> defines
command characteristics: O - mandatory for all devices, D -
additional, C - specific. Column <> represents
hex code loaded into the instruction register.  Commands marked
asterisk, supported for compatibility with
old controllers.   In the columns <>
The following designations are accepted: CY - cylinder registers, SC -
sector counter register, DH - device number register and
heads, SN - sector number register, FR - property register.
The use of registers is indicated as follows: y -
registercontains parameters for the command (for register number
devices and heads - both parameters are used), D -
only the device number is used, d - only the
device number, use of the head number field is specific
for the manufacturer, D0 - the command is addressed to device-0, but
both devices perform it.                                    
                                                                
                                 Table 3. ATA-2 command system
+-------------------------+--------+---+-------+--------------+
|                          |        |   |       |Spanish registers|
|         Command |Protocol|Type|  Code +--+--+--+--+--+
|                          |        |   |       |FR|SC|SN|CY|DH|
+===========+========+===+======+==+==+==+==+==+
|ACKNOWLEDGE MEDIA CHANGE -|        |   |       |  |  |  |  |  |
|confirmation of change of wear-|   VS | D |  DBh |- |- |- |- |D |
| body |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|BOOT - POST-BOOT - loading-|        |   |       |  |  |  |  |  |
|ka media (after loading-| VS | D | DCh |- |- |- |- | D |
|ki) |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|BOOT - PRE-BOOT- loading|   VS | D |  DDh |- |- |- |- |D |
|media (before loading) |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|CHECK POWER MODE - check-|   ND | D |98h ESh|- |y |- |- |D |
|ka consumption mode |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|DOOR LOCK - lock the door-|        |   |       |  |  |  |  |  |
|tsu (prohibit change wear-| VS | D | DEh |- |- |- |- | D |
| body) |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|DOOR UNLOCK - unlock |   VS | D |  DFh |- |- |- |- |D |
| door |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|DOWNLOAD MICROCODE - |        |   |       |  |  |  |  |  |
| loading internal microcode |   P.O. | D |  92h |y |y |y |y |D |
|software |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|EXECUTE DEVICE DIAGNOSTIC |   ND | O |  90h |- |- |- |- |D*|
|- diagnostics |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|FORMAT TRACK - format-|   VS | C |  50h |- |- |- |- |d |
| track|        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|IDENTIFY DEVICE - identify-|   PI | O |  ECh |- |- |- |- |D |
|fixation of the device |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|IDLE - transition to state|   ND | D |97h EЗh|- |у |- |- |D |
|waiting |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|IDLE IMMEDIATE - immediately-|        |   |       |  |  |  |  |  |
| transition to state |   ND | D |95h E1h|- |- |- |- |D |
| expectations |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|INITIALIZE DEVICE |        |   |       |  |  |  |  |  |
|PARAMETERS - initialization|   ND | O |  91h |- |y |- |- |y |
|device parameters |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|MEDIA EJECT - extract |   ND | D |  EDh |- |- |- |- |D |
|carrier |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|NOP - idle command |   ND | D |  00h |- |- |- |- |у |
+-------------------------+--------+---+-------+--+--+--+--+--+
|READ BUFFER - reading |   P.I.| D |  EChh |- |- |- |- |D |
|buffer |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|READ DMA (w/retry) - |   DM | D |  C8h |- |y |y |y |y |
|reading via DMA with repetitions |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|READ DMA (w/o retry) - |   DM | D |  C9h |- |y |y |y |y |
|reading via DMA without repeats|        |   |       |  |  |  |  |  |
+-----------+--------+---+-------+--+--+--+--+--+
|READ LONG (w/retry) - |        |   |       |  |  |  |  |  |
|<> reading from the surface |   PI | D |  22h |- |y |y |y |y |
| tori |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|READ LONG (w/o retry) - |        |   |       |  |  |  |  |  |
|<> reading without |   PI | D |  23h |- |y |y |y |y |
|repetitions |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|READ MULTIPLE - multiple |   PI | D |  CChh |- |y |y |y |y |
| vein reading |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|READ SECTOR(S) |        |   |       |  |  |  |  |  |
|(w/retry) - reading sect-|   PI | O |20h |- |y |y |y |y |
|moat with repetitions |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|READ SECTOR(S) |        |   |       |  |  |  |  |  |
|(w/retry) - reading sect-|   PI | O |  21h |- |y |y |y |y |
|ditch without repetitions |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|READ VERIFY SECTOR(S) |        |   |       |  |  |  |  |  |
|(w/retry) - verification-|   ND | O |  40h |- |y |y |y |y |
|reading sectors from the surface |        |   |       |  |  |  |  |  |
|torami |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|READ VERIFY SECTOR(S) |        |   |       |  |  |  |  |  |
|(w/retry) - verification-|   ND | O |  41h |- |y |y |y |y |
|reading sectors without |        |   |       |  |  |  |  |  |
|repetitions |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|RECALIBRATE - recalibration|   ND | D |  1xh |- |- |- |- |D |
|(search for zero track) |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|SEEK - search |   ND | O |  7xh |- |- |y |y |y |+-------------------------+--------+---+-------+--+--+--+--+--+
|SET FEATURES - installation |   ND | D |  EFh |y |- |- |- |D |
|properties |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|SET MULTIPLE MODE - |        |   |       |  |  |  |  |  |
|installation of multiple |   ND | D |  Cbh |- |y |- |- |D |
|mode |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|SLEEP - translation into <> |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|STANDBY - transfer to duty |   ND | D |96h E2h|- |y |- |- |D |
|ny mode |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|STANDBY IMMEDIATE - immediately-|        |   |       |  |  |  |  |  |
| transferred to duty |   ND | D |94h EOh|- |- |- |- |D |
|mode |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|WRITE BUFFER - writing to |   P.O. | D |  E8h |- |- |- |- |D |
|buffer |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|WRITEDMA (w/retry) |   DM | D |  CAh |- |u |u |u |u |
+--------------------------+--------+---+-------+--+--+--+--+--+
|WRITE DMA (w/o retry) - |   DM | D |  CBh |- |u |u |u |u |
|recording by DMA without repetitions|        |   |       |  |  |  |  |  |
+--------------------------+--------+---+-------+--+--+--+--+--+
|WRITE LONG (w/retry) - |        |   |       |  |  |  |  |  |
|<> record with full |   PO | D | 32h* |- |in |in |in |in |
| by tors |        |   |       |  |  |  |  |  |
+--------------------------+--------+---+-------+--+--+--+--+--+
|WRITE LONG (w/o retry) |        |   |       |  |  |  |  |  |
|<> entry without |   PO | D | 33h* |- |in |in |in |in |
|repeat |        |   |       |  |  |  |  |  |
+--------------------------+--------+---+-------+--+--+--+--+--+
|WRITE MULTIPLE - |   PO | D | CSh* |- |у |у |у |у |
|multiple recording |        |   |       |  |  |  |  |  |
+--------------------------+--------+---+-------+--+--+--+--+--+
|WRITE SAME - record with |   PO | D |  E9h |u |u |u |u |u |
|breeding|        |   |       |  |  |  |  |  |
+--------------------------+--------+---+-------+--+--+--+--+--+
|WRITE SECTOR(S) |        |   |       |  |  |  |  |  |
|(w/retry) - record secto- |   PO | O| 30h* |- |in |in |in |in |
ditch villagerepetitions |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|WRITE SECTOR(S) |        |   |       |  |  |  |  |  |
|(w/o retry) - record sec- |   P.O. | O | 31h* |- |y |y |y |y |
| tori without repetitions |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|WRITE VERIFY - record with |   P.O. | D | ZCh* |- |y |y |y |y |
|verification |        |   |       |  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
|Vendor specific - snecifi-|        |   |  8xh |  |  |  |  |  |
|logical commands (optional- | VS | C | 9Ah |- |- |- |- |- |
| Manufacturer's opinion) |        |   |OOh-СЗh|  |  |  |  |  |
|                          |        |   |FOh-FFh|  |  |  |  |  |
+-------------------------+--------+---+-------+--+--+--+--+--+
   *Codes are maintained for compatibility.                     
                                                                
 ATA-2 devices implement their main purpose using
read and write data commands, minimum addressable unit
which is a 512-byte sector.                            
   Commands for reading sectors in PIO exchange modes - READ SECTOR(S)
and DMA - READ DMA allow you to read sequentially located
sectors,the number of which is specified in the SC register, and the address
the initial sector - in the CH, CL, D/H and SN registers. Teams
readings have versions with or without repetitions. In the first case,
if an unrecoverable error is detected while reading a sector,
The device automatically makes several retries
reading.  After the command is executed in case of a fatal error
the block of command registers contains the address of the sector on which this
an error has occurred.   If the device uses ECC code, then
It corrects some reading errors without repetitions, but
indicates this fact in the error register.                       
   Read command in block transfer mode READ MULTIPLE
differs from the usual one (with PIO exchange) in that requests
interrupts are generated not per sector, but per block
sectors, the size of which is specified by the SET MULTIPLE MODE command.
Additionally, if a fatal read error occurs
the contents of the command register block will be undefined (not
will indicate a bad sector).  Block mode by reduction
number of interrupts that the processor must service, in
multitasking system allows for increased productivity
disk sharing even by 30%.  Depends on the block size
exchange performance, but the size value is optimal for
devices, maybedo not coincide with the value optimal for
operating system.  In a single-tasking system, essential
there will be no gain from block mode, since interrupts can
and not to be used.                                            
   The <> read command READ LONG reads a data sector
along with control bytes and also has versions with repeats and
without.  When ee is called, the SC register must indicate the request only
one sector.  The data block is read in 16-bit words, and
control bytes are 8-bit.  Some ATA-1 devices
unable to quickly transmit ECC bytes following data. For them
reading must use 8-bit exchange in PIO mode
Mode 0.                                                         
   Verification command READ VERIFY SECTOR(S) with and without repetitions
Unlike normal reading, it does not transfer data from the device. B
if an unrecoverable error is detected at the address of the bad sector
indicates the contents of a block of command registers.   Request
interrupts are executed after the command is executed.                
                                                                
                    To be continued...