ZX Power #02 24 мая 1997

Iron - Microprocessors Zilog: Z80, 1980, Z8000, Z80000.

         Microprocessors

         family Zilog

        Z80, Z8000, Z80000.

(P) Fisherman
________________________________


       Microprocessor Z80.


  Development of microprocessor Z80
firms based on Zilog microprocessors 8080/8085, but it 
introduces several additional features. Z80 microprocessor is 
used in home computers, and industrial controllers.


   This microprocessor compatible
Up to the microprocessor 8085 to
system commands and machine code, ie it can perform
programs written for the microprocessor 8085. However, the 
compatibility in the other direction not always achieved due to 
the presence of additional commands in the Z80. 

   Z80A microprocessor works
at 4 MHz frequency synchronization, and
microprocessor Z80B - at a frequency
to 6MGts.


     Contact function Z80.


  Contact function microprocessor Z80 is shown in Figure 1. Bus
data had not multiplexed address bus and a half,
as is done in the microprocessor 8085. In connection with this 
reduced number of lines of control bus, In particular there are 
only three interrupts: RESET, INT, NMI (Non-maskable). However, 
this reduction does not lead to severe restrictions, since the 
signal INT may divide the set

interrupting device firm
ZILOG.

  In the microprocessor Z80 is no internal timing generator, 
and therefore require external chip timing generator.



        Microprocessor Z80.

                #

    A11 <- January 1940 -> A10

    A12 <- February 1939 -> A9

    A13 <- March 1938 -> A8

    A14 <- April 1937 -> A7

    A15 <- May 1936 -> A6

    CLK -> June 1935 -> A5

    D4 <-> July 1934 -> A4

    D3 <-> August 1933 -> A3

    D5 <-> September 1932 -> A2

    D6 <-> October 31 -> A1

    5V -> November 30 -> A0

    D2 <-> December 1929 <- GND

    D7 <-> 13 28 -> RFSH

    D0 <-> 14 27 -> M1

    D1 <-> 15 26 <- RESET

    INT -> 16 25 <- BUSRQ

    NMI -> 17 24 <- WAIT

    HALT <- 18 23 -> BUSAK

    MREQ <- 19 22 -> WR

    IORQ <- 20 21 -> RD


              Figure 1


   The meaning of most signals
obvious from their mnemonics, such BUSRQ (bus request) and BUSAK
(Confirmation of bus request), but
signal RFSH (regeneration is unique to the CPU company Zilog. 
It becomes active between the teams and helps in the 
regeneration of dynamic RAM, which are connected to the CPU 
buses. 


  Microprocessor architecture.

Internal registers of the CPU Z80:

  the main alternative

     A, F A ', F'

     B, C B ', C'

     D, E D ', E'

     H, L H ', L'

     I interrupt vector

     regeneration of the memory R

     index register IX

     index register IY

     stack pointer SP


   Working registers are similar
respective registers 8085,
but the Z80 there is an additional second set of registers 
(A'-L ') and a second status register (F ').

Having a second set of registers
greatly facilitates the work with
calling routine, or ISR, because the programmer can use them 
for an alternative set, avoiding the main contents of the 
register saving programs, such as commands PUSH exceptions to 
the stack. 8-bit register of the interrupt vector I used for 
the localization of CP ISR start address when the CPU

operates in one of three modes
interrupts.

   Initial ISR addresses are as follows:
 RESET - the PC is loaded 0000h;
 NMI - the PC is loaded 0066h

         Mode 0 CPU allows

         contents of the vector transformation
         closing the I;
 INT - Mode 1 in the PC loaded
         zhaetsya 0038h; mode

         2 CPUs seek to
         initial address in the cell
         Since the XXYY (here XX Be
         is taken from the vector interrupt
         tion I, and YY is introduced

         The data bus from the interruption
         yuschego device).

   To transfer the CPU in interrupt mode 0,1 or 2 of the program
requires a special command,
eg IM 2. When you set Mode 2 interrupt device (eg, PIO, or CTC) 
should be initialized for 8-bit value YY, which is returned CPU 
to generate an interrupt. 

   Register R regeneration Memory
operates in conjunction with the signal
RFSH the regeneration of dynamic RAM. After each team
is the increment register
R and its contents shall be issued for
the lower half of address bus
between the teams.

   Two 16-bit index registers IX and IY provide a
commands index addressing mode.


   Support circuitry.


   Parallel I / O PIO -
chip is designed to transfer data via 8-bit
ports to external devices.

   Serial I / O -
UART UART used
chips instead of PIO, when you want to send 8 bits of data
one sequence, rather than
eight parallel lines. Used to connect to computers displays in 
the lines of communication between computers, as well as for 
some printers. 

  Timer / counter CTC - a programmable counter, in which the 
CPU can download and retrieve information. Usually,

CTC-chip is from 1 to 4
counters. Sometimes one counter
may be included in a chip
PIO.

   To work with the CPU Zilog Z80 company produces chips PIO, 
CTC and dual chip UART (called DART).



        Application Z80.


   Z80 microprocessor is used in many personal
their household (SinclairZX81, Sinclair
ZX-SPECTRUM, Tandy TRS80) and office (Sharp MZ80, Research 
Machines RML380L, Icarus Superbrain) computers. 

Single chip microcomputers.


   In a family of single chip
Zilog Z8 microcomputer firms
includes several fast and powerful processors. A typical 
microcomputer consists of ROM / EPROM 2 or 4 Kbytes, RAM 144

bytes, UART, two counter / timers, and four ports (32 
input-output signals). 

   The family includes:
Z8601-ROM, 2 Kbytes and reduced

   device;
Z8611 - 4 KB ROM - / -;
Z8602 - without the ROM building with 64 con
   tact and the memory bus;
Z8612 - 4 KB ROM - / -;
Z8603 - 2 Kbytes of ROM, EPROM 2

   KB and above the mouth
   REFER;
Z8613 - 4 KB ROM - / -;
Z8671 - 2 Kbytes ROM, given

   above the device and interpretation
   torus tiny-BASIC.

   The instruction set of microprocessors Z8 is completely 
different from instruction set microprocessor

Z80. Each processor Z8 contains 144 bytes of internal register 
ZUPV.Eti registers include the addresses of I / O (Eg, ports, 
timers, or UART), as well as 124 general purpose working 
registers, all of which can operate as accumulators or index 
registers, and 0.1 ports, you can use to access the address 
buses and data, if you want to expand the memory or input / 
output. 


   Z80 microprocessor was in
Book Ricordi Gines, as the most
the widely used processor!


  MICROPROCESSOR FAMILY

            Z8000.


   The family firm Zilog Z8000
includes some 16-bit CPU
differing only
addressable memory (including virtual memory), and several
auxiliary circuits, such as input-output control and
soprotsessorov.Osnovnymi CPU are:
Z8001, addressable memory 8 MB
 (16 7 address lines) with 16-bit data bus and Noah (48-pin
 housing type DIP);
Z8002, addressable memory 64 Kilo bytes (16 address lines) with 
16 bit data bus (40-of the contact housing type DIP). Memory 
management unit Z8010 is used in conjunction with the CPU

Z8001 to control targeted
8 MB of space, thus providing a displacement
segments and protection pamyati.Mikroprotsessory Z8003 and 
Z8004 almost identical to the Z8001, but they are not allowed 
to arrange virtual memory. 


   Contact function Z8001.


     Microprocessor Z8001

 AD0 <-> January 1948 <-> AD8
 AD9 <-> February 1947 <-> SN6
 AD10 <-> March 1946 -> SN5
 AD11 <-> April 1945 <-> AD7
 AD12 <-> May 1944 <-> AD6
 AD13 <-> June 1943 <-> AD4
 STOP -> July 1942 -> SN4
 M1 -> August 1941 <-> AD5
 AD15 <-> September 1940 <-> AD3
 AD14 <-> October 1939 <-> AD2
 Vcc --- November 1938 <-> AD1
 VI -> December 1937 -> SN1
 NVI -> 13 36 - GND
 SEGT -> 14 35 <- CLOCK
 NMI -> 15 34 -> AS
 RESET-> 16 33 -> DECOUPLE
 MO <- 17 32 -> B / W
 MREQ <- 18 31 -> N / S
 DS <- 19 30 -> R / W
 ST3 <- 20 29 -> BUSAK
 ST2 <- 21 28 <- WAIT
 ST1 <- 22 27 <- BUSRQ
 ST0 <- 23 26 -> SNO
 SN3 <- 24 25 -> SNI


            Figure 2


   Figure 2 shows the function
Contact Z8001, 40-pin
Z8002 has no signal rates
segment (SN0-SN6) and interrupt
in violation of the segment (SEGT).
Each CPU family Z8000 forms a Z-bus consisting of address 
signals, data and control in which the transmission of data 
between the CPU and memory or input-output.


   All CPUs have a multiplexed address bus / data, and address 
strobe signal AS indicates the presence of the bus address 
information. Signals segment number SN0-SN6 the CPU Z8001 act 
as additional address line, by increasing the binary code on 
these lines by switching to other segments of 64 Kbayt.Chetyre 
status signal ST0-ST3 deciphered in 16 discrete signals 
assisting in the distribution of individual memory spaces for 
programs, data and steka.Eto particularly useful in the CPU 
Z8002, because it allows to extend the address range of 64 
Kbytes. 

  Note the presence of a microprocessor family Z8000 following
additional signals:
a) except the reset signal RESET
 There are four signals of interruption: NMI (Non-maskable), NVI
 (Nevektornoe), VI (vector) and
 SEGT (segmentation violation).
 Last interrupt is used when connecting to the CPU Z8001
 memory management unit;
b) BUSREQ and BUSAK organiza tion for direct memory access;
c) signals the state of B / W (bytes /
 word), N / S (Regular / System
 mode) and R / W (read / write)
d) control signals M1 and M0,
 calculated on a consistent
 inclusion, which provide
 one CPU access to the divided
 device in a multiprocessor
 environment.


  Microprocessor architecture.

 Available: 16-bit registers:
R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
R10, R11, R12, R13, R14, R15 - block
working registers, which can be
used as accumulators and index registers
(Except R0).

   Registers R0 ... R7 calculated
for processing bytes and words. Allowed unification of the 16 
registers in 32-bit register pair

limited treatment of 64-bit
data. Programming counter consists of a 16-bit offset and 
7bitnogo rates segmenta.Ukazateli conventional (R14) and 
systemic (R15) stacks, batteries and index flags and 
registry.Slova management. Programming the counter.

A pointer to a new area of ​​the state program. Counter 
regeneration. 

   CPUs can work in your system
and normal (they are similar to supervisor mode and user CPU 
MC68000). The current regime is determined by the bit in the 
status register. For each mode Separate the stack pointer, 
represented by the two registers R15 (plus 7 bits in two

Registers R14). In the system mode has access to additional 
commands, such commands IO. Therefore, in the multiprogramming 
environment program user (running in normal mode) to perform 
the tasks I / O request must

operating system (running
in system mode). From the Z80 microprocessor architecture to 
keep a counter in the recovery for dynamic RAM. 

  Pipelining, using "queue" commands, as in microprocessors 
8086/8088, not here, but but the CPU Z8000 introduced

Early interpretation of commands.
It allows for interpretation, regardless of the chosen mode of 
addressing. 

   Memory byte, and
bits A0 selects one of two
8-bit banks with even or
odd addresses. The length of each operation code is slovu.Kody 
operations and data words always begin on even addresses memory.



         SYSTEM commands.


   9 addressing modes:
Register: LD R4, R7;
Direct: LD R4, 5;
Indirect register: LD R4, (R2)

   (Download the contents of R4

   memory cell whose address is

   in R2);
Direct: LD R4,% 1800 (download

   R4 contents of the memory cell

   1800h);
Index: LD R4,% 4000 (R1) (zag
   ruzit in the R4 cell contents

   memory whose address is

   4000h amount and content of R1)
Base: LD R4, (R6) (4) (loaded
   zit in the R4 cell contents

   memory whose address is

   the amount of displacement of 4 and contents
   On the register R6);
Base-index: LD R4, (R5) (R12)

   (Download the contents of R4

   memory cell whose address is

   equal to the sum of the index of the R12 and

   databases from R5);
Relative: JR +17 (go to

   PC +17);
Implicit addressing: LDCTLB FLG,% 31

   (Load 31 bytes of registers

   control).


   The system commands the CPU family
Z8000 below. Mnemonics
instruction mnemonics recall the microprocessor Z80, which is 
evident from the following example program:



        LD R1, #% 643

        LD R2, <<3>>% 5000

        ADD R2, R1

        OUT 3, RL2

1.Zagruzit in R1 decimal number locally 643.
2.Zagruzit in R2 content
 memory cells of segment 3 offset 5000h.
3.Pribavit R1 to R2;
4.Vyvesti younger half-R2 in
 I / O port with address 3;

MANAGEMENT AND VIRTUAL MEMORY.


   To control the address range 8 MB in the CPU chip is used 
Z8001 Z8010 management pamyatyu.Ona converts 23-bit logical 
address from CPU in 24-bit physical address, delivered to the 
address translation pamyat.Dlya involved over 7 bit SN6 on SN0, 
which using the table form a 16bit ID block (block size 256 
bytes). Low 8 address bits are fed into the memory without

transformation.

   Physical addresses provide access to 64 memory segments, 
whose size ranges from 256 to 64 Kbytes. Due to the memory 
management unit MMU Z8001 has followingManufacture advantages:  
1.Obem physical memory system may be less than

required for all programs of logical memory. Device MMU
can run two different programs with the same
range of logical addresses,
directing them to different areas
physical memory. In the multiprogramming environment, the 
operating system can reschedule the physical memory to perform 
program in a free area memory.

 2.In the MMU is allowed to appoint
each segment a number of attributes for memory protection, such 
as only readable, with a restricted

DMA access or only for the operating system.

   Memory management system
can also be implemented
convenient for multiprogramnoy
in virtual memory, in which the external memory is
extension of the main pamyati.Virtualnaya memory is typically 
used in large and medium-sized computers. Operating System, 
memory management unit and drive together to provide for

custom programs greater physical addressable memory.

   For specific program / segment in the MMU is box notifying 
the CPU (interrupt) and causing reprogramming MMU to transfer 
additional segment from disk into memory. MMU device should 
release memory space for this additional segment, temporarily 
moving the other segment on the disc. Such operations in the 
memory of "invisible" for user programm.Chtoby implement 
virtual memory firm Zilog Z8003 CPU predalagaet and Z8004. 


  Support circuitry.


  With the Z8000 microprocessor can use the 8-bit CPU support 
chips Z80 (PIO, SIO and STC), if demux bus address / data. But 
for 16-bit CPU company Zilog produces two new families

auxiliary circuits:
- DEVICE Z-bus with the numbers
 Z80XX, which are connected to
 Tyres Z8000, including complex and multi bus address / data;
- Universal device but measures Z85XX, which chayutsya 
connected to the CPU without the multiplex  Bus address / data.


   Peripheral Products:
 for univ-e
Z-bus function

Z8016 Z8516 DMA controller
Z8030 Z8530 - / - posled.svyazi
Z8031 Z8531 - / - async th -/Z8036 Z8536 Counter / Timer and

   Parallel input-output
Z8038 Z8538 the interface

  Input-output [FIFO]
Z8060 Z8560 and the FIFO

   Dilator Z-FIO
Z8068 ----- processor encrypt
               tion data
Z8070 ----- processor with a plate
               equation describing the point
Z8090 / 4, Z8590 / 4 - Universal
peripheral controller.

   CPU Floating Point
Z8070 (FPU) classifies firm Zilog
to the so-called extended
processor architecture, and calls EPU (CPU extension).
It connects to the CPU buses and perform arithmetic operations
over floating-point numbers,
working alongside TsP.Protsessor floating-point control command 
stream with CPU, identifying and fulfilling their

command. Although the internal format
FPU corresponds to 80-bit floating-point transmission
data between the CPU by bytes and words.


  MICROPROCESSOR FAMILY

           Z80000.


   32-bit compatible CPU Z80000
up with 16-bit microprocessor family Z8000 (Z8001 and
Z8002). Apparently, in the part of domestic capacity, he is
the most powerful 32-bit microprocessor, since it has
internal cache memory, and memory management unit and its 
frequency synchronization of 25 MHz. In this device has 6-stage 
pipeline, and the performance of the CPU corresponds 4-5 
million operations per second. 

CPU consists of:
- 64-bit registers:
 RQ0, RQ4, RQ8, RQ12, RQ16, RQ20,
 RQ24, RQ28;
- 32-bit registers:
 RR0, RR2, RR4, RR6, RR8, RR10,
 RR12, RR14, RR16, RR18, RR20,
 RR22, RR24, RR26, RR28, RR30,
 the pairs, for example, RR28, RR30
 form a 64-bit register RQ28
 etc.
- Registers the status of the program;
- Default stack pointer;
- Registers descriptor table
 transformation;
- Stack pointer overflows;
- Control Register Hardware
 interface;
- Long call management systems dark configuration.


   As in previous microprocessors, is surgery performed on byte 
(8 bits), words (16 bits), long (32 bit) and very long (64 bit) 
words. One bit in flags of government (ie the register state) 
defines the work of the CPU normally or in system mode.

Some teams, such as I / O is performed only in
system mode (when it works
operating system).

   The contents of status register
program - is a memory address, from when an interrupt loads the 
value in the software counter and in the word flags and 
management. One of the four descriptor table register

Conversion memory management unit uses a memory addressing. 
Stack pointer overflow is drawn when

an error calculating the address during a termination. Longword 
Management system configuration includes

bits that determine the function of internal cache memory and 
the device memory management.


   The system commands the CPU Z80000
save complex commands previously
considered microprocessors
such as command block transfer and search strings. In the device
are nine addressing modes, and in the calculation of addresses
may participate base register, index register, and register 
offset. Defined in team memory address is interpreted in one of 
three ways depending on the state of two bits in a word flags

and management:
1) a compact representation - 16
 bit (allows addressing 64
 KB);
2) the segmental representation - 32
 bit (15 bit segment with 16
 bit offset for the first 2
 GB or 7-bit 24-bit
 shift for the next 2
 GB);
3) a linear representation - 32
 bits (addressing 4 GB).

   In the segment representation
address calculations only affect the bias field.

   Address specified in the command
called a logical address,
a memory management unit
converts it into a physical adres.Preobrazovanie as follows:
1) involving the internal
 buffer conversion, where the storage nyatsya tag addresses and 
information function of the last 16 pages to  which produced 
the inversion of similarly cache to Mand / data; 2) if the 
buffer does not transform  a relevant tag, then

 CPU accesses to the tables transformation in memory, using
 To do this, one of the four re Giustra descriptor table, and
 then transmits the required information tion on the buffer 
element transformation, to which the longer  just did not 
appeal. 

   In addition, the memory management unit provides a means of 
protection, such as treatment only to perform, permission

reading and writing.

   The internal cache memory is
of 16 elements of 16 bytes each. It records information
of 16 memory cells, which
occurred last treatment
When the cache is obtained
"Blunder" when selecting the team of
adjacent memory cells transferred
the whole package, which optimizes
the process of reading from memory.

   Microprocessor Z80000, as
its 16-bit predshedstvenniki,
works with processors expand EPU (ie coprocessor).
Coprocessor is the floating-point
Z8070 works with 16 - and 32bit CPU. By Z80000 can be connected 
and other auxiliary chips, such as controller

DMA Z8016. To connect the components into larger configurations
Zilog firm uses its
standard called Z-bus.


  Zilog company is developing the new 64 bit microprocessor 
compatible up with their predshedstvennikami.


  Work is also underway on the development of RISC processors.


           Dictionary.

DIP - building a two-way

   Pin: mill
   dard shell chips.
DMA (Direct Memory Access) - a direct
   access to my memory: the transfer

   data between memory and introduce
   home-finding without the participation of the CPU.
ISR (Interrupt Service Routine)
   interrupt service procedure
   tion: a program that performs
   Xia in response to an interrupt.
PC (Program Counter) - Programming

   Counter: CPU registers containing
   schy address should be done
   my team.
MMU (Memory Management Unit) -

   DEVICE memory management

   Memory Manager: Internal

   means the processor prednaz
   The values ​​for the control dos
   obtuse to physical memory.


          Literature.

Holland R. "Microprocessors and
Operating Systems: Summary
handbook "Per.s Eng.
________________________________