Scrap Metal - about the structure of the 6912 screen from a hardware point of view.

About the structure of the 6912 screen
 Once again about the structure of the 6912 screen
 (this time from a hardware point of view)

Lord Vader 

                 Introduction

   Unusual screen structure of the ZX Spectrum
It is customary to explain from a programmatic point of view─
niya - they say, after suffering a little and calculating
address of an acquaintance, maybe later enough
quickly print a character using a type procedure
LD A,(DE):INC E:LD (HL),A:INC H, after th─
go, suffering a little more and recalculating
familiarity address to attribute address, you can
easy to color it.
   Without at all denying these considerations─
Niya, I’ll try to clearly explain why─
mu and from a hardware point of view, the screen is semi─
thought the same. In order to completely
you need to understand my reasoning
have some idea of how
dynamic memory works (the same one
which PYS, RU7, etc.), or at least
have an understanding of digital circuit technology─
Nick in general. It is important to clarify that in this
The article simply outlines the widely known (in
narrow circles...) facts, she does not pretend
for originality.

   Looking at the ZX Spectrum 48k circuit...

   As you know, Sir Sinclair was a businessman─
but rather, let's say, economical. Next─
Therefore, it can be assumed that everyone
component in the ZX Spectrum circuit (original─
flat! Clones have nothing to do with it, and in general, in 
82 they are not yetwas also in the project!) was 
selected on the basis of the greatest cheapness
provided that he can still perform
at least somehow its functions, albeit not the best
way.
   Let's take a closer look at the VI microcircuits
de-memory (video memory I call what
known as 'slow memory') is 
4116-15, clones of Intel chips are more dynamic─ 
Sky memory 2116, 16 kilobits each. Well,
like PYS, only four times less capacious. A
at the same time, like the i8080, requiring three pitas─
niy -+5, +12 and -5 volts: in 82 NMOS-
triple power supply chips have long been out of date
fashion and have become consumer goods - I understand─
It’s clear that 8 outdated microcircuits with a little bit more
the false BP turned out to be cheaper than 8 normal─
ny DRAMs with one power supply.
   '-15' in the chip name means
access time (in tens of nanoseconds) - than
The larger this number, the slower the chip, i.e.
15 is 150 ns. You can find it on the Internet 
datasheet for TMSCh116-15 (one of the clones) and
find out all the temporary buildings from there.
   So, what do we see from this data─
ta: a full memory access cycle does not last
less375 ns('access time'150 ns- time
from the beginning of the cycle until data is received). Ok─ 
cursing up to a whole number of clock cycles 7 MHz
(140 ns each), we get the access cycle
duration 3 cycles 7 MHz. For time 1
familiarities (8 pixels with a frequency of 7 MHz)
we need to select 2 bytes, and if we
we spend 3 clock cycles on sampling each, then
will remain free only2 clock cycles 7 MHz
(1 clock Z80) - no access for pro─
processor while sampling a row of pixels
one could not even dream...

           Altwasser's trick

   However, a hint on how to improve the situation─
tion, contained directly in the datasheet for 4116,
and it's called 'page mode'. Page mode -
this is when RAS is introduced into the chip once
address, after which a series of images is made─
tions at constant RAS=0 (and corresponding
at a constant RAS address), strobed─
by a sequence of CAS pulses, with
In this case, it is only possible to change the CAS part of the address─
sa. From the timelines in the datasheet it follows that
You can access two different CAS addresses
produce in4 clock cycles 7 MHz, which corresponds─
Two2 cycles Z80.
 The fact that ULA (actually ULA
-it's an abbreviation for 'uncommitted logic' 
array', and call the video controller that way 
ZX Spectrum is incorrect, but what? 
let's say if everything is around, for example, Atari or 
Commodore, gave proper names to their 
custom chips, but not Sinclair Research?) 
accesses video memory this way, you can
confirm in different ways. One of them
- take an oscilloscope, or better yet, logs─
ical analyzer and plug it into the ZX board
Spectrum. Another is to buy a book about $$$ 
about how they broke UL and read it there.
   I chose the 'sofa' method - I took ka─
some VHDL-model UL's on the Internet─
rneta (which was found by DimkaM and which,
in fact, is a clone of UL's TK90X), 
stuck it in the simulator, screwed it to it about─
humble testbench and forced the simulator
draw pictures with simulated signals─
mi.
   Since in this article I am aware─
I'm not going to dwell on the question in detail
'contended memory', that is, the issue is delayed─
processor socket in the branded ZX Spectrum,
when it accesses video memory in time─
Data sampling name for the next iso line
fermentation, then in the picture you will only see
cycles of UL access to video memory.

   Before continuing, let me clarify the principle─
address multiplexing principle in RAS and
CAS addresses of dynamic memory: how easy it is
see from the ZX Spectrum diagram (you need to look
multiplexer that connects the ShA Z80 and 
chip address busvideo memory), mla─ 
low bits A6..A0 - this is the RAS address, high
A13..A7 - CAS address.  Main reason
exactly this distribution is
that the Z80 processor can perform rege─
neration of dynamic memory chips times─
approximately 16 kbit, while it outputs content─
regeneration counter pressure (the same re─
hyster R) just for the low-order bitsA6..A0
SHA. Moreover, such a distribution for
video memory is useful because in the process you─
Full screen screen regeneration of all rows
memory in microcircuits will happen more than once
times: for example, when sampling 6912 screens re─
generation occurs 6 full times.

   So, see fig. 1, where the beginning is shown
samples the topmost line of video memory:



                  Fig. 1

   The first address sent to the chip
- zeros (which corresponds to a byte at address
#4000 ), during the second sampling only changes
CAS address -#30, which corresponds to a byte
at#4000+#30*128=#5800. This way─
om, a byte of pixels is sampled and
byte of attributes. Close to this sample,
lasting 2 cycles Z80, the next one comes, in which─
secondbytes are selected#4001 and #5801 (from─
only the RAS address has changed). Total ULA tra─
tit 4 clocks Z80 per sample 4 bytes video─
memory for 2 acquaintances, the remaining 4 clock cycles
remain free for possible appeal─
nia Z80.
   It is the sampling grouping of 4 bytes per ma─
in the shortest time possible, I got it down─
no possible appeal of the Z80 during you─
Borki and it is this group that is responsible─
for the pattern6-5-4-3-2-1-0-0, pov─
repeated every 8 cycles Z80 (which is on
At first glance it seems paradoxical).
   From all of the above it follows important
output - each byte of pixels along with co─
the corresponding attribute byte must
lie in memory according to the same RAS-
address (i.e. have the same minor 7
address bit). It's easy to see the structure
screen satisfies this property - hell─
res of adjacent bytes of pixels within
familiar places differ by 256 and have ml─
Low byte of the address, identical to the low byte
byte address of the attribute byte.

 Thus, not only 'convenience' is not
Chat familiarity on the ZX screen identified it
structure, hardware considerations as well
played an important role.