I2C bus - I’ll tell you today about the bus used in “their” TVs.

AY-Track: Rosenblum!                                          
By: Macros,1Odec2000,Kotlas/Limenda!                          
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 I'll tell you today about the tire used -
mine is on “their” TVs. This tire has
is needed only
                                             
                                                    
                                                    
                                                    
 (Inter Integrated Circuit)        
                                                              
 So this is bidirectional asynchronous
serial data bus,
something like our rs-232. The bus contains
two lines: data line (SDA) and line
synchronization(SCL). This mode is implemented
is achieved through use in power circuits
sources with a three-stable output, which
allows you to connect peripheral devices to the bus
devices directly.  It can
be CMOS, NMOS and bipolar devices.
The total capacity of the bus lines must be
no more than 400 pF. Input capacitance for each
blowing the chip should be within the range of
5 to 10 pF, permissible connection length
The number of lines in the bus is no more than 2 m.        
 Data is transmitted in groups of bits (coded
words), one additional bit - per
as acknowledger (ACK). Before we start
data transmission signal and synchronization
routing lines are in a state
log."1".  The beginning of the transmission is the level
log."0" on the data line.                  
 Reception of information from the data line occurs
dits at log level "0" in the synchronization line
tions. At the moment the ninth bit arrives
the data line remains in state
log."1", and from the receiver along the same line
a bit receipt arrives with a level
log."0".  The transfer ends when
the level corresponds to both lines
log."1".                                 
 The completed data packet consists of non-
how many bytes?  After the start bit in
line to the consumer, the address is sent (7
bit) of the block - the addressee to whom it is intended
this information has begun. The eighth bit op-
divides the regimenext code word,
i.e.  will it be transmitted from
next node (“0”) or accepted as required
bitem - addressee ("1"). handshake
the bit comes from the last
the block that has finished receiving data.  If
the eighth bit had the value "1", then accepting
The sender sends the addressee becomes the source
information and sends its data to the same
mu master node.                        
 At maximum clock frequency Ft=100
kHz bus information flow rate
is 10 kB/s.                   
 This bus is used in television technology
uses to exchange mukpokE9troller with
memory and other external devices.