Deja Vu #06
30 сентября 1998
  Железо  

drop of solder - Additional graphics mode 512x192.

<b>drop of solder</b> - Additional graphics mode 512x192.
SoundTrack: BY MR.Z / EX'LS / HARDWAVE
__________________________________________


(C) V.M.G. Kharkov, Ukraine.
__________________________________________


Additional graphics mode - 512x192
-----------------------------------------


   The proposed mode allows you to position the screen 512 
pixels per line or 85 characters with a matrix of 6x8, which 
will accommodate a much larger amount of information and make 
it more convenient to work with text, monochrome graphics 
terminal programs.


   The numbering of elements in the diagram of the circuit 
given the Pentagon (by VMG) and may not match your scheme. 
(Numbered from the address signals A0 to A15). 



                       C1> 2 A0 MUX
 RES> 1 R T 2-D3> 5 A1

               August 5-D15> 11 A2 Y1 4> 9-D41/D42

  D1> 2 D GND> 14 A3 Y2 7> 5-D5
 SEL> 3 9 C Y3> C30 and 1-D7

               June 1-D2> 3 B0 Y3 12> 11-D17
 +5 V> 4 S D1 C1> 6 B1

                      +5 V> 10 B2

       VD1 VD2 9-D15> 13 B3 D1 - 1533TM2
 C29> <> D2 - 1533KP11

                             1 AB

       1K 15 OE D2
 +5 V>> 3-D8

                                             "1-D40


    Diodes - KD522


 (Output>) to signal a withdrawal of forming his chips;
 (Pin <) to apply for withdrawal of a new signal,
cutting off the old one.

   Signal SEL - proinvertirovanny signal
9-O ID7.


           Connecting 1533ID7:


signal contact m-we

  A12 1

  A13 2

  A14 3

  A3 4
 DIRQ 5 (a signal IORQ passed through the controller FDD)

  A15-6
 -SEL 9 (the desired signal, which must be inverted)


   Takzhe on top of the D38 should be soldered
D38 '(1533IR23) all outputs connected
with D38, and the inputs connected to respective outputs D37. 
At the 1 st conclusions D38 and D38 ' the signals C3 and 2-D3, 
and 11 th conclusions signals C29 and C3, respectively. Also, 
the findings 9,12,15,16,19 chip D40 should be a 1K resistor to 
submit the land. 

   Further development enabled by setting bit
1 port # EFF7 on and off or RESET
discharge of the same bits. After inclusion
memory is formed two areas-# 4000 - # 57FF
- Even bytes on the screen, and # 6000 - # 77FF -
odd bytes on the screen. The second screen is addressed to the 
same (# C000-# C800 and # E000 # E800). 



      Location of bytes on the screen

      ----------------------------



        4000 6000 4001 6001 4002 6002 ... 401F 601F



   In a nutshell, how the scheme. When
inclusion of the extended screen, the output register (s) begin 
to shift into contact with double the frequency. When the loop 
is executed (Read-byte image read / write byte attribute) 
instead of bytes of attribute reads byte image of the second 
half of the screen to address # 6000. Read it in an additional 
register, which clings to parallel basic register for a byte of 
image data (in this scheme, they are referred to as D38 and D38 
'). Register byte storage attribute is translated in the 
Z-state, and that he not provided in lieu of flowers 
RND-sequence, its output through resistance props to the ground 
and +5 V. 




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