Nicron #25 20 марта 1997

Железо

Iron - an overview of the microprocessor Zilog Z380, continued.

                       MPU Z380


(C) WLODEK BLACK

[End. Beginning in room 7].



    Management tact of wait
when referring to the lower, upper
      and secondary memory

When using the built-in controller memory access
(WCP) can programmatically set the artificial delays in the 
engine cycles of treatment to specific habitats for WCP lower, 
middle and upper memory.

The structure of the control registers delays the same for all
areas of memory:


       7 6 5 4 3 2 1 0


     T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0


"T1", "T2" and "T3" is the number of machine cycles of a 
machine cycle, and "W2", "W1", "W0" - binary constant weight 
programmable delay: for example, an entry in the register 
value% 10100000 asks the delay in cycle T1 at 101% = 5 
additional cycles. 


  Economical mode of shutdown

Z380 has a software-controlled shutdown mode is economical,
using which one can achieve a sharp reduction in processor 
power and / or a microprocessor. If the regime economically 
stop (REO) is allowed to activate REO performed with the 
command processor SLP (sleep). After performing SLP stop 
listening to the clock outputs BUSCLK and IOCLK; signal at the 
output / STNBY becomes logic 0, indicating confirmation of REO, 
processor ceases execution of operations; address bus goes into 
a logic 1; control bus takes third state. Signal / STNBY can be 
used to feed the team a power failure or other devices at least 
for locking of the external clock. Exiting REO effected by the 
reset of the request Non-maskable interrupt of the request 
masked interrupt any type (if permitted EI), as well as a 
request to the capture of tires if one is allowed in the 
register SR. If the REO is not resolved, the team SLP is 
executed as HALT (including exposure confirmation signal / 
HALT). REO management by using the control register

REO and return from REO (SMCR). (Address SMCR in EP 
UVV-00000016h). 


       7 6 5 4 3 2 1 0


     STBY BRXT - - - WM2 WM1 WM0


Appointment of digits SMCR:

STBY - logic 1 enables the transition to the EMR;
BRXT - logic 1 enables the output of the EMR at the request of 
the capture of Tyre; WM2 ... WM0 - set the delay time in the 
periods of the fundamental frequency clock, during which the 
processor will be held in "limbo" state (literally, "WM" - 
Warm-Up time, that is "warm-up time) after leaving the RER, 
this time may be necessary for the entry into operation of 
other devices, disconnected the signal / STNBY. Installing a 
logic 1 sets the bit WM0 delay 2 ^ 16 clock periods, WM1 - 2 ^ 
17, WM2 - 2 ^ 19. During the warm-up time listening to the 
pulses of clock outputs and BUSCLK IOCLK not performed. For all 
logic 0 delay is incorrect. 


      Interrupt system

Interrupt System Structure (PO) Z380 contains compatible with
Z80 and Z180 subgroup, and also includes new elements,
For example, interrupt handling code to the wrong team.
Hardware interrupts are caused by feeding low-level
one of the inputs / NMI, / INT3../INT0.
/ NMI - Non-maskable interrupt input. When handling NMI 
processor sends a return address stack, stores the flag 
resolution maskable interrupt disables interrupts masked and 
moves to address 00000066H, that is similar to Z80. The 
difference is that the NMI in the 380-m is not the highest 
priority (!) - primarily served by a software interrupt to the 
wrong code team (trap). The third level of priority is 
interrupted by the entrance / INT0, which is completely 
analogous to the usual masquerading interrupt Z80. In 
particular, this input supported 4 types of interrupt IM 0, IM 
1, IM 2, IM 3. Mode 3 is different from IM IM 2 only using 
16-bit vector and the offset: bits A31 .. A16 are given 
extended registers I, and bits A15 .. A0 are read from the data 
bus in cycle interrupt acknowledgment, in received address is 
read a word or long word (depending on the mode of the 
processor), which also serves as the address of the transition 
to routine servicing. Interrupts / INT1, / INT2, / INT3 (in 
descending order of priority) caused by feeding low levels of 
the corresponding input, and address the processing procedure 
is determined by the so-called associated vector, which is 
calculated as follows: A31 .. A16 are taken from the extended 
register I; A15 .. A9 determined by the contents of register 
AVBR (his address to the EP UVV 00000018H); A8 = 0; A7 .. A0 
are, respectively, (16-hex form) 00H for / INT1, 04H - for the 
/ INT2, 08H - for the / INT3. According to the calculated 
address is read a word or long word (depending on the mode of 
the processor), which also serves as a jump address to the 
serving process. 

AVBR:

       7 6 5 4 3 2 1 0


     AB15 AB14 AB13 AB12 AB11 AB10 AB9 0


Enable / Disable maskable interrupts by either
teams EI 0 ... EI 3 / INT0.../INT3, either by direct 
manipulation of the interrupt enable flags, which are in 
Register IER (Interrupt Enable; address in the EP UVV 
00000017H) and in the register SR (bit 5). Distribution of 
responsibilities between the IER and the 5 th bit SR is as 
follows: IER bits indicate only the possibility of interruption 
from a particular input / INT 0 .. 3 and 5-th bit SR - this is 
interrupt enable flag. Team DI can be at once to ban all masked 
interrupts. EI enables interrupts, but only those that are 
unlocked in the IER. 

IER:

       7 6 5 4 3 2 1 0


      - - - - IE3 IE2 IE1 IE0

                   0 0 0 1