Nicron #20 14 февраля 1997

Железо

Iron - an overview of the microprocessor Zilog Z380, continued.

                          MPU Z380

[Continued. Previous publications - in numbers 18,17,16,15,14,
12,11,10,9,8,7]

(C) WLODEK BLACK


    Memory management using
    built-in controller memory access

It should be noted immediately that use built-in controller
Memory (WCP) is not necessary. If the speed of the RAM 
corresponds to the CPU clock if the external circuit sample of 
memory devices provide all the necessary electrical signals, 
the existence of the Communist Party can not even guess. Using 
MAC as appropriate, apparently, either in the most simple 
devices with a static RAM, or if there is slow devices in the 
memory. 

   Z380 supports two schemes of signal sampling
memory device (Memory Chip Select) within the lower 16?
address space. The first scheme provides for the use of 6 
signals sampling devices, memory allocation address space as 
follows: 

00FFFFFFH
    / UMCS Top
                  Memory


               Not used

    / MCS3 Average
                  memory-3

    / MCS2 Average
                  memory-2

    / MCS1 Average
                  Memory-1

    / MCS0 Average
                  memory-0


               Not used

    / LMCS Lower
                  Memory
00000000H


The second scheme provides 3 signal sample memory devices
with the distribution of address space according to the picture:

00FFFFFFH
    / UMCS Top
                  Memory



    / MCS Average
                  Memory



    / LMCS Lower
                  Memory
00000000H


When using the MAC can be programmed artificial
tightening cycles of memory access for an additional 1, 2 or
3 cycles separately for the lower, upper and middle memory. When
using the first scheme in the average memory subdivided into 4
area, each of which can also establish its
delay. Such a construction of memory useful, apparently
using devices with different speed, which
obvious. But the signals / RAS and / CAS for dynamic RAM MAC 
does not develops.


            Lower memory

Lower memory starts at address and is defined 000000000H
bits 7 ... 4 registers LMCSR0 and all the bits of the register 
LMCSR1.Eti bits set bits address bus, which should be analyzed

for issuing a signal / LMCS. The logic of analysis is this: if 
the register bit = 1, the bit address bus is checked for 0. If 
at least one comparison revealed bit address bus = 1, then 
signal / LMCS is not produced and tightening cycles is not 
satisfied. In other words, to activate the sample the lower 
memory needed to all the specified bits of address bus were 0.


            Register LMCS0:

     MA15 MA14 MA13 MA12 0 0 0 ERF

MA15 ... MA12 - bits determine the bit A15 ... A12 address bus;
ERF - enable bit lower recovery of memory: 0 - not allowed;
1 - in a cycle of regeneration signal / LMCS is activated by 
contact addresses of regeneration in the range of low memory. 
RESET resets to 0. 

            Register LMCS1:

     MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16

MA23 ... MA16 - bits determine the bit A23 ... A16 bus address.

Example: when setting bits MA23 ... MA12 in a range of lower
memory "extends" from 0% to 111 111 111 111 (# 0FFF), that is, 
only within the 4K. 

[To be continued].