Echo #07 31 октября 2000

Железо

DMA Sound Card - Programmable timer 8253 (Continuation of topic DMA SC in the ECHO 6).

      Programmable timer 8253

   (Continuation of topic DMA SC in ECHO 6)



   To set the time intervals and the formation of signals with 
different time parameters used programmable

timer 8253 (domestic analogue
KR580VI53) or 8254. From a programmer's standpoint they are 
identical. The composition of the timer includes: a buffer data 
bus, the circuit input-output control and three independent 
channels, each of which contains a mode register, a control 
circuit channel, buffer, and 16-bit counter.


   Programming the channel by
by output control words to register
channel mode and the initial value in its
counters. Each channel has a control
GATE input and output OUT and can work in
one of the following six modes:

   - Mode 0 (interrupt terminal
account). After recording a control word in
mode register channel output OUT is set low voltage;
download counter does not change this state. Then begins the 
decrement counter (Serial subtraction of his unit). At a time 
when the counter is reset at OUT output voltage is set using a 
high-level and stored prior to loading counter the new value. 
Account possible only when a signal of high level

input GATE. The low level of the signal or the drop-down front 
prohibit expense. 

Restarting the counter during counting leads to the following: 
loading the low byte stops the current account, the download 
high byte starts a new cycle of bills. The minimum value of the 
counter is 2.


   - Mode 1 (Single shot). On
output OUT is formed by a negative pulse of duration t = n * T, 
where n-number loaded into the counter, T-period clock

pulses. Low level output OUT
installed with the next cycle after
feeding the input signal GATE high level.

   Download to counter the new numbers do not
affect the duration of the current pulse
and takes into account the next time. Restarting the counter is 
growing Front entrance GATE (without restarting the counter). 
The minimum allowable n = 1. 

   - Mode 2 (frequency generator). Each
again after reaching a count of zero on
OUT output appears negative pulse with a duration of one clock 
cycle. Restarting the counter effect only after restart the 
counter. The disappearance a high level signal at the input GATE

terminate the account and at the output OUT is fed
High Voltage. Restart
counter is in the presence of input
GATE signal is high.

   - Mode 3 (square wave generator). Same as mode 2, but the 
positive output level occupies the first of half RIOD, and a 
negative second-half period. More precisely, if n (the initial 
value of the counter) is even, then the duration of the 
positive and negative half-cycles is equal to n * T / 2;

if n is odd - the (n +1) * T / 2 and (n-1)
* T / 2 respectively. Low signal
input GATE prohibited by, the output
OUT signal is set high. GATE allows a high level of account and
growth runs counter to the initial state. Note that n = 3 in 
this mode is unacceptable. 

   - Mode 4 (event counter). At the end of the reference number 
that is loaded into the counter, at the output OUT is formed by 
the negative pulse per cycle. Record in

counter during counting the low byte is not
affect the current account and write a senior
byte count restarts. Low level input disables GATE score, 
highest - permits. The minimum allowable value

counter is 1.

   - Mode 5 (event counter with auto-load). Unlike Mode 4 is
that each increase of input signal
GATE restarts the counter. Perezagruka
counter does not affect the current cycle, but
the next cycle is determined once again poised number.


   Time diagrams of timer mode

   presented at the next figure:



   CLK

   __ N = 5 n = 4

   WR


   GATE


   OUT

   n 5 4 3 2 1 0 4 3 2 2 1 0


   Mode 0



   CLK

   __ N = n = 5 4

   WR


   GATE


   OUT

   n 4 3 2 1 0 5 4 3 5 4 3 2 1 0


   Mode 1



   CLK

   __ N = 4 n = 3

   WR


   GATE


   OUT

   n 4 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0


   Mode 2



   CLK

   __ N = 4 n = 5

   WR


   GATE


   OUT

   n 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 5 5 4


   Mode 3



   CLK

   __ N = 4 n = 5

   WR


   GATE


   OUT

   n 4 3 2 1 0 5 5 4 3 2 1 0


   Mode 4



   CLK

   __ N = 4

   WR


   GATE


   OUT

   n 4 3 2 1 0 4 3 4 3 2 1 0


   Mode 5


   In the sound card has two timers,
addresses are listed in the table below:


   First Timer:


      Operation Address Assignment


       # 3D recording Download Counter Channel 0

                 Reading Reading counter channel 0

       # 7D record Downloading counter channel 1

                 Reading Reading counter channel 1

       # BD recording Download Counter Channel 2

                 Reading Reading counter channel 2

       # FD Record Control Word

                              in the mode register channel



   Second Self-Timer:


      Operation Address Assignment


       # 3E record Download Counter Channel 0

                 Reading Reading counter channel 0

       # 7E record Downloading counter channel 1

                 Reading Reading counter channel 1

       # BE record Download Counter Channel 2

                 Reading Reading counter channel 2

       # FE Record Control Word

                              in the mode register



   Control word format is as follows:


   7 6 5 4 3 2 1 0


                        Layout mask bits


                 0: 0 = binary code, and 1 '

                      1 = BCD code

                 > 1-3: The mode of operation of the channel: a 
'0Eh 

                          000 - Mode 0

                          001 - Mode 1

                          X10 - Mode 2

                          X11 - 3 mode

                          100 - Mode 4

                          101 - Mode 5

                 > 4-5: Type of load meter: a '30h

                          00 - "latch"

                               (Bits 0-3 are indifferent)

                          01 - only the lower byte

                          10 - only the most significant byte

                          00 - Low byte, then senior

                 > 6-7: number of channels: a 'C0h

   00 - Channel 0

   01 - Channel 1

   10 - Channel 2

   11 - Prohibited combination


   There are two ways to read the current
counter value of the channel:


   1. Reading to stop the counter. For
ensure a stable reading is necessary to suspend the channel or 
supply low-level signal at the input GATE (except mode 1) or 
blocking clock.


   2. Reading "on the fly." To read
counter without stopping the process of sending the account 
used to port 43h control words in the "lock" (see above).

This control word captures the current
the counter and you can read it
low byte, then high byte.



   In the sound card channels have a timer
next appointment.


   First Timer:

 Channel Assignment Mode


   0 request for channel 0 DMA 2, CLK = 3.5 MHz

   1 request for a DMA channel 2, CLK = 3.5 MHz

   2 Interrupt Request 2, CLK = 1.75Mgts

             (Bit vector D6)



    Second Self-Timer:

 Channel Assignment Mode


   0 request for DMA channel 2 2, CLK = 3.5 MHz

   1 request for channel 3 DMA 2, CLK = 3.5 MHz

   2 Interrupt Request 2, CLK = 1.75Mgts

             (Bit vector D5)



   GATE inputs of all channels are always
high level, so at the expense of channels
always allowed.

   Attention! DMA and interrupt controllers
normally work only if the corresponding timer channel operates 
in the 2-m mode. Therefore, you must first program the timer, 
and then authorize the transfer of DMA or interrupt timer.