Born Dead #0E 19 декабря 1999

Программирование

Anger Day-II - features work with registers of I / R in the processor Z80: excerpts from official documents.

                        Topical-II


(C) Mac Buster ^ XTM
(C) UnBEL! EVER ^ XTM

About a year ago, Ivan Roshchin together with the release of 
next version BEST VIEW published a short research note on

he found a bug (undocumented feature) in the
Z80 processor commands in the aspect of the interrupt.
The sensation was that described by Ivan the test can be
was 100% define - running your program under the emulator
or on a live machine. In view of the rarity of this
"Undocumented" phenomenon, no emulation of those times did not
worked exactly as behaved real Z80.

Time passed ... It was found that in the past, programmers or
knew, or guessed incorrectly setting a flag in IFF2
If the arrival interrupts at run-time commands LD A, R, or
LD A, I. Judge it can be quite clearly by the code
programs written long before the 98-th year. Most
Emulator is now support this feature
Z80, but there is only one question: "Why in 20 years
protsecsora existence of this phenomenon did not become 
property of the broad the mass public, along with half of the 
index registers, Double prefixes and a host of other, so-called

undocumented?? "

The answer to this tragic ... We live in a state of this
Information hunger! " It is because of lack of access to
primary sources is a constant opening of America.
That is, imagine that you are the owner of Hi-End
VCR, but to him no instructions. And year after year
you press the mute button controls and gradually become aware 
of their the true function. Likewise, the player looks silly 
trying to understand what lies behind the keys to sound mode

PAUSE at the famous ELITE. And because he could not even 
imagine could come, that the document attached to ELITE 
corporate governance all described in detail ...


In short, ladies and gentlemen! If you want to spend time
study of well-known things - please! But it may be
should stretch and get all the same last instruction
operation??

This is what Mac Buster ^ XTM, when not feeling sorry for $ 5, 
ordered in the firm Zilog guide processor Z80. And of course

the result surpassed all expectations! The following is a 
translation several key manual pages that have a direct

relating to "bug'u Ivan Roshchina.

----------[ Top ]------------------------------------- -------- 
Zilog MP Z80 (R) User's Guide 
-------------------------------------------------- 
-------------                                                   
        LD A, I  Operation: A <-I


 Operator: LD

 Operands: A, I


            +-+-+-+-+-+-+-+-+

            | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED

            +-+-+-+-+-+-+-+-+


            +-+-+-+-+-+-+-+-+

            | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 57

            +-+-+-+-+-+-+-+-+

 Description: The contents of the register of the interrupt 
vector is loaded I 

            in the battery.


              M Cycles T States MHz E.T.

                  2 9 (4.5) 2.25

 Effect on the flags:


             S: Set if the seventh bit in register I is 1;

                 otherwise cleared

             Z: Set if the register I = 0, otherwise cleared

             H: Cleared

           P / V: Contains a copy of the trigger interrupt IFF2

             N: Cleared

             C: Not affected

Note: If an interrupt occurs at the time of execution of this
team flag overflow / parity (P / V) will contain 0.
-------------------------------------------------- ----[ A5-23] 
- Zilog MP Z80 (R) User's Guide

-------------------------------------------------- -------------
                                                          LD A, 
R 

 Operation: A <-R

 Operator: LD

 Operands: A, R


            +-+-+-+-+-+-+-+-+

            | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED

            +-+-+-+-+-+-+-+-+


            +-+-+-+-+-+-+-+-+

            | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 5F

            +-+-+-+-+-+-+-+-+

 Description: The contents of the register R is loaded memory 
upgrade 

            in the battery.


              M Cycles T States MHz E.T.

                  2 9 (4.5) 2.25


 Effect on the flags:


             S: Set if the seventh bit in register I is 1;

                 otherwise cleared

             Z: Set if the register I = 0, otherwise cleared

             H: Cleared

           P / V: Contains a copy of the trigger interrupt IFF2

             N: Cleared

             C: Not affected

Note: If an interrupt occurs at the time of execution of this
team flag overflow / parity (P / V) will contain 0.
-------------------------------------------------- ----[ A5-24] 
- The family of Zilog Z80, Questions and Answers: MP Z80

-------------------------------------------------- -------------
Q: I'm not sure that getting true value of state

   interrupts when I use the instruction LD A, I and LD A, R for

   read IFF2. Why is this happening? How to deal with it?

A: The CMOS version of the Z80 CPU, we have corrected the 
problem. But in the Z80 CPU 

   NMOS version, under certain circumstances, trigger

   Interrupt IFF2 Z80 processor does not always show the real

   state of the interrupt.

Two instructions - LD A, R and LD A, I copy the trigger status
IFF2 interrupt flag in the parity / overflow (P / V), and
modify the contents of accumulator Z80 (see table 7.0.1 in the 
"Z80 CPU technical manual ").


Thus, we can determine whether you are allowed or disallowed
interruption during the execution of one of these teams. This
necessary to obtain reliable information on the
machine. Nevertheless, if the termination occurs during the
perform one of these instructions (assuming
interrupts must be enabled), the flag P / V cleared
(Reset to 0). This will lead to an incorrect interpretation - 
ostensibly interrupts have been banned at the time of the 
statement. 

This paradox can be explained by a sequence of actions
when the internal functions of the processor. Case that
in this situation, the secondary trigger interrupt (IFF2) 
cleared even before its contents are sent in a flag P / V.


Trigger status interrupt is not copied into the parity flag to
appearance acknowledgment signal interruption that occurs
during the execution of instructions. Since the validation 
mechanism receive interrupt automatically clears the trigger 
interrupts, then parity flag is also cleared, despite the fact 
that the interruption were resolved at the beginning of 
instruction execution. 

The easiest way to define a situation based on the fact
the fact that in the event of interruption to the top of the 
stack recorded at least one element - the old value of PC. So

way, by writing a zero value at preceding
current top of the stack, just before the execution of command
LD A, I (or LD A, R) and checking this value immediately after 
it performance, we can establish the true value of the trigger

interrupts. If this value is changed during execution of LD
A, I (or LD A, R), then interruption occurred during the
execution of this command, and interrupts are definitely 
allowed. Here sequence of actions taken advantage which can be

write a procedure to determine the status of interrupts:

 - Zero out the word that precedes the current top of stack
 - Run the command LD A, I (or LD A, R)
 - Immediately check the state of the flag P / V. If it is 
installed, 

   then we have no reason to doubt that

   interruption and in fact allowed
 - If P / V is reset, then it makes sense to us to check the 
status of 

   words before the top of the stack and if it is not zero, 
then this 

   means that the interrupt is still allowed and at the time of 
execution 

   LD A, I (or LD A, R) is interrupted. If the word

   before the top of the stack has not changed - it's safe

   say that the interruption and in fact prohibited

Both of the following procedures return the flag C is 
discharged into If the interrupt request, or to establish if 
they prohibited. Procedures for changing the contents of 
register A, but it is not necessary expect that the output it 
will contain important I register, or R. The value of other 
flags is undefined. 

The first procedure can be located anywhere in memory than
"Zero page" - from # 0000 to # 00FF. This small
limitation is only that the procedure only checks
byte word from the next position stack. This byte is not
will be zero after the arrival of an interrupt only if the
procedure itself is not in the "zero page". The second
procedure checks both at the same position next byte stack, and
thus relieved of such a restriction.

Attention! These procedures assume that the interrupt handler
enables interrupt upon completion of their work. This is done in
most cases. However, you may receive an incorrect
result if the procedure is an interrupt handler, which does not
permit termination upon termination of their work will
executed immediately after execution of instruction LD A, I
(Or LD A, R).


  Listing 1: This procedure does not work from the addresses # 
0 - # 00FF 


   GETIFF:

         XOR A; C flag, acc.: = 0

         PUSH AF; stack bottom: = 00xxh

         POP AF; Restore SP

         LD A, I; P flag: = IFF2

         RET PE; Exit if enabled

         DEC SP; May be disabled (P flag: = 0).

         DEC SP; Has stack bottom been

         POP AF; overwritten?

         AND A; If not xx00h, INTs were

         RET NZ; actually enabled.

         SCF; Otherwise, they really are

         RET; disabled.

         END


  Listing 2: This procedure can work from any address


   GETIFF:

         PUSH HL; Save HL contents

         XOR A; C flag, acc.: = 0

         LD H, A; HL: = 0000h

         LD L, A;

         PUSH HL; Stack bottom: = 0000h

         POP HL; Restore SP

         LD A, I; P flag: = IFF2

         JP PE, POPHL; Exit if enabled

         DEC SP; May be disabled (P flag: = 0).

         DEC SP; Let's see if stack bottom

         POP HL; is still 0000h.

         LD A, H; Are any bits set in H

         OR L; or L?

         POP HL; Restore old contents.

         RET NZ; HL <> 0: isn't enabled

         SCF; Otherwise they really are

         RET; disabled.

   POPHL:;

         POP HL; Exit when P flag is

         RET; set by LD A, I (P flag: = 1).

         END

----------[ End ]------------------------------------- ---------
So, dear readers, all have long been an open and
documented ... We can only again encourage you
read corporate governance in general, to take information from
primary sources. Moreover, that these same source material is 
quite available with the advent of InterNet'a.