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ZX Pilot #41
29 декабря 2002 |
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Iron - Programming Guide itself cool sound card - DMA USC.
D M A I
Ultrasound Card
--== Єє The Best for SPECCY ЄЄ ==-
+------------================------------+
Greetings,
Dear reader ZxPilot'a!
Today we begin to publish
Programming Guide itself
cool sound card - DMA USC for
coolest computer - Zx-Spectrum!
So, in this part of the guide will help you
acquainted with how the same card
~ ~ Sees the memory and using what leverage to
it refers to.
+------------================------------+
Programming Guide
DMA UltraSound Card
1. Distribution of computer memory.
Before I go right up to the issue
programming card, you must at least
learn a little about how she
distributes computer memory that is available
her. Access DMA controller (i8237) to
memory does not depend on expansion port RAM
(# 7ffd, # 1ffd, 'etc) and the only information available to him
memory is divided into pot-sized to 64
kB.
To cite this particularly slow-witted
risunochek, that you were able to compare division
RAM company to Z80, and for DMA:
Memory Z80 Memory DMA
Home Address Address Bank
----------------
0 # c000 # 0000 # 2000 Bank
Page # ffff # 3fff
----------------
1 # c000 # 4000
Page # ffff # 7fff
----------------
2 # c000 # 8000
Page # ffff # bfff
----------------
3 # c000 # c000
Page # ffff # ffff
----------------
4 # c000 # 0000 # 2001 Bank
Page # ffff # 3fff
----------------
.. ... ..
----------------
7 # c000 # c000
Page # ffff # ffff
----------------
.. ... ..
and so on ...
In a word bank consists of 4
pages and begins with a page
number divisible by 4 (0, 4, 8, etc.). Thus
a computer with a 128 kilo will be only two
banks, with 512 - 8 cans, I have for example
1024 KB - 16 cans. Addressing within the bank
ranges from # 0000 to # ffff, then
is to say shestnadtsatibitnaya.
For memory management, there
registers banks and registers the start address, and for each
channel they own.
2. DMA controller registers.
2.1. Register banks.
Each channel has its own register bank
so access to the channel memory does not depend
banks to other channels.
Destination address
# 0777 Register Bank 0go channel
# 1777 1st channel register bank
# 2777 2nd channel register bank
# 3777 third channel register bank
When programming the registry
want to assign to him the bank number to
that must be addressed.
Example:
...
ld bc, # 0777; register 0go channel
ld a, 1, programmed to
out (c), a; work with 1m Bank
...
2.2. Register start addresses.
This register sets the starting address from
which will begin transmission unit
data. Register contains 16 bits and
determines the address within a given bank.
Each channel has its own FPU register
start address.
Destination address
# 0c77 register early. Address 0go channel
# 2c77 register early. Address 1st Channel
# 4c77 register early. Address 2nd channel
# 6c77 register early. addresses the third channel
When programming, given the two bytes
addresses sequentially - first junior
bytes, then a senior.
Example:
...
ld bc, # 0c77; the register addresses 0 Canal.
ld hl, # 1234; load address of # 1234
out (c), l; current bank
out (c), h
...
2.3. Current address register.
In addition to the initial address register
are current address register.
The initial value is entered in this
register simultaneously with the register
start address. Later in the course
transfer value of the current address
automatically increase or
decreases depending on the mode
channel (see mode register).
Appeal to the current address register
made to the addresses of registers
start address in read mode
values.
Opportunity to read the value of the current
address of the register to "fly" gives
opportunity to do such things as
voicemeter or oscilloscope.
2.4. Register initial counter
cycles.
In this case given the initial
number of cycles to transfer
Programmable channel.
Destination address
# 1c77 register early. counter 0go channel
# 3c77 register early. Counter 1st Channel
# 5c77 register early. Counter 2nd channel
# 7c77 register early. counter the third channel
When programming this register
must specify the length of a block of data on
1 byte less than the true length, ie at
transfer 100 bytes of data in the register should
record number of 99.
Example:
...
ld bc, # 1cff; in the count register
ld hl, # 1234; 0go channel fills
out (c), l; length of the transmitted
out (c), h; block
...
2.5. Register current cycle counter.
The register contains the current value
cycle counter (number of remaining cycles
transmission). It appears in the number of cycles
always one less than the number has not yet
transmitted data elements.
Appeal to the registers of the current counter
cycles performed at the addresses of registers
initial loop counter in read mode
values.
to be continued ...
+------------================------------+
On this, perhaps, everything. Expect
continuation of this novel and do not forget
that the contents of this section of the newspaper
ZxPilot depends only on you! Ask
questions, and we here at them and reply!
You can contact us on the following
addresses:
Mikhalchenkov Dmitry
Post-Mail:
85280, Ukraine, Donetsk region,
Dzerzhinsk, pos. Kirov,
st. Youth, Building 16, Apt. 48
E-Mail:
mehanik@nv1.novdz.donetsk.ua (for Dima)
vadim@novdz.donetsk.ua
(Subj: to gl.energetika)
+------------================------------+
D M A II
Ultrasound Card
--== Єє The Best for SPECCY ЄЄ ==-
Zdorovenki boule!
Greetings to you, the reader ZxPilota!
So you waited for the continuation of this
Uncategorized. As they say - not passed
century) A reason for this was a lot! The first and
the most weight - STE your zero
activity, Mr. Reader!, (I just
I do not know what to write about, here are a couple more
articles give the editor, but on it: (
Well, okay, I'm so distracted.
Today we'll talk about registers
mode commands, masks, and the state. Thus,
go ...
2.6. Mode register.
This register sets the operation mode
his channel controller. Has address
# Bc77. Register bits have the following
destination:
7 6 5 4 3 2 1 0
0-1: Number of channels:
00 - 0-channel
01 - 1st
10 - 2nd
11 - 3rd
2-3: Opening hours:
00 - test
01 - Recording (in memory)
10 - reading (from memory)
11 - Invalid
combination
4: Avtoinitsializatsiya:
1 - enabled
0 - disabled
5: Change of address
in the exchange:
0 - an increase
1 - decrease
6-7: Type of transmission:
00-Transfer Mode
on demand
01-mode single
transmission
10-mode block
transmission
11-cascade mode
Briefly explain the purpose of some
bits:
■ Number of channels - the choice of channel DMA
mode is specified.
■ Operation - for DMA USC
used only two modes:
- Reading from memory (a combination - 10) -
when you play a sample, or when
moving block of data in memory
(Defined for the channel source).
- Memory write (komb. - 01) - at
moving the unit, set of spacecraft
signal-receiver.
■ Avtoinitsializatsiya - in other words -
loop, ie at the end of the transfer
recover the original data
start address and block length. Thus if
we establish the 4th-bit register, then we
soluble rebroadcast again.
■ Changing the current address. When
zero state of this bit when sending
address increases, ie, sample will be
played ok, otherwise -
decreases addresses.
■ Transmission Type: BIS i8237 (KR1810VT37)
supports 4 modes of transmission, but
to work with the DMA USC, we need only
one - a single mode transmission
(Combination 01). This mode is
that after the transfer the next byte
data card frees the CPU bus,
but immediately begins to scan signals
request and as soon discovers
active request signal initiates
next transmission cycle.
>!!!< Remaining modes in this
manual describes will not be because of
narrow focus of the article. If someone
interesting to a full description of LSI included in the
card, please contact the author.
2.7. Instruction register.
This register controls the operation of
controller and is programmed only one
time to be fully initialized. Has address
# 8c77. The layout of the register:
7 6 5 4 3 2 1 0
0: 0-transfer ban
memory-memory
1-resolution
1: 0-fixing ban
addresses 0m channel
1-permit
2: 0-release
controller
1 block
3: 0-normal
timing diagram
1-time compression
transmission
4: 0-mode fixed
priorities
1-mode cyclic
shift of priorities
5: 1-mode extended
record
0-delay recording
6: 0-active high
signal level query
1-Low DREQ
7: 0-active high
signal
confirmation
request for PDP
1-Low
To work with sound all the bits
Register set to 0-th state.
Other combinations are used to working with
blocks of data for transfer, fills
... but talk about it separately.
2.8. Mask register.
Before programming a
channel you want to prevent him to perform
current work, for this it should be
disguise. And in order to enable the
channel after programming it needs to be
unmask. For these operations, the DMA
be two registers:
1.Registr mask (# fc77) - masks /
unmasks all DMA Channels. Bits 0-3
register correspond, respectively, for 0-3
channels. 0 in the corresponding bit permits
work, and 1 - prohibits.
2.Registr single mask (# ac77).
2 1 0
0-1: Channel number.
2: 0-permit work,
1-ban.
2.9. Status register.
Register reflects the current state
inquiries and transfers for all four
channels. Bits 0-3 are set to
unit after the completion of the transfer of
Channels 0-3 (bit 0 - channel 0, bit 1 -
channel 1, etc.), unless specified mode
avtoinitsializatsii. These bits are cleared
after the command to reset the controller after
each read operation of sostoyanoya
status register. Bits 7.4 point on
which of the channels 0-3 is active in the current
time request signal to the FPU.
That's all. Regards,
Dmitri aka
Hard / WCG
+-------------=====[ Cut ]=====------------+
Ask us questions or just so
can be reached at:
Mikhalchenkov Dmitry
Post-Mail:
85280, Ukraine, Donetsk region,
Dzerzhinsk, pos. Kirov,
st. Youth, Building 16, Apt. 48
E-Mail:
mehanik@nv1.novdz.donetsk.ua (for Dima)
vadim@novdz.donetsk.ua
(Subj: to gl.energetika)
+------------================------------+
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