AY-3-8910 - Reprinting information on a coprocessor known to you.

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║ AY-3-8910.           ║
╙─────────────────────────────── ───────────────────────────────╜
(R) Klim Gromov

 I don’t claim copyright here, this is just a reprint
for information on the coprocessor you know.
    I understand that this information is outdated, but nevertheless
may be useful to someone in a text version, and for others it
not at all.  Therefore, I bring to your attention a reprint from
ZXS user manual, information on music
processor AY-8910.

 ┌───────┐
ground potential 01 ──┤- +├── 40 Ucc
not used 02 ──┤ ├── 39 TEST1
analog channel 'B' 03 ──┤< >├── 38 analog channel 'C'
analog channel 'A' 04 ──┤< <>├── 37 DAO
not used 05 ──┤ <>├── 36 DA1
              IOB7 06 ──┤<> A <>├── 35 DA2
              IOBb 07 ──┤<> Y <>├── 34 DAZ
              IOBS 08 ──┤<> <>├── 33 DACH
              IOBCh 09 ──┤<> 8 <>├── 32 DAS
              IOBЗ 10 ──┤<> 9 <>├── 31 DAb
              IOB2 11 ──┤<> 1<>├── 30 DA7
              IOB1 12 ──┤<> 0 <├── 29 BC1
              IOBO 13 ──┤<> <├── 28 BC2
              IOA7 14 ──┤<> <├── 27 BDIR
              IOAb 15 ──┤<> ├── 26 TEST2
              IOAS 16 ──┤<> <├── 25 A8
              IOACH 17 ──┤<> <├── 24 A9
              IOAZ 18 ──┤<> <├── 23 RESET
              IOA2 19 ──┤<> <├── 22 CLOCK
              IOA1 20 ──┤<> ├── 21 IOAO
                          └───────┘

 Purpose of microcircuit pins
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^

DAO-DA7 - data/address bus with three states. Conclusions
                30-37 in AY-3-8910.

This 8-bit bidirectional bus is designed to forward
addresses and data between the processor and the PGZ itself. In data mode
DA7-DAO corresponds to bits B7-B0 of the generator register area
tora.  In the address mode DAZ-DAO, the number of the selected re-
hyster (0-17), and DA7-DACH in combination with address inputs A8 and A9
form the leading part of the address.

A8 and A9 (input) -Address buses A8 and A9. Conclusion 25.

The PGZ memory area consists of 16 8-bitwords included in
composition of the system's total 1024-word memory. Just with the help of these
address buses and the PGZ memory addressing is expanded from 256
(DA7-DAO) 1 to 1024 words. If the memory size of the real system
The "PGZ-computer" does not allow the use of these buses, then they are not
are connected during installation of the system because each of them is equipped
internal supporting (for A8) or quenching (for A9) resistor.
If these buses are not used in “noisy” environments, it is necessary
so that they are connected to a common bus “+5v” and “ground”, respectively
responsibly.

RESET (input) -Pin 23.

Used to initialize the PGZ and install its blocks in use
running state by applying a logical zero to the output. When
In this case, the entire register memory area of the PGZ is reset to zero. You-
The water is equipped with an internal retaining register.

CLOCK (input) -Output 22.

Used to supply a clock frequency that sets the timing parameters
Parameters of the noise, tone and envelope generators. TTL input
compatible.

BDIR, BC2, BC1 (inputs) -Pin 22.

 Control buses - BUS DERECTION, BUS CONTROL 1,2. Using
are used to control all external and internal bus operating
tions in PGZ. The signals for these buses are generated directly
coherentprocessor CP1600.
    If using a different processor, these signals must
be generated by similar bus signals of the used pro-
processor or simulated on the input/output buses of the main micro-
system processor. Decoding of control signals is given
in the table.
 ╔══════╦══════╦═════ ═╦═════════════════╗
        ║ BDIR ║ BC2 ║ BC1 ║ CP 1600 FUNCTION ║
        ╠══════╬══════╬═════ ═╬═════════════════╣
        ║ 0 ║ 0 ║ 0 ║ NACT ║
        ║ 0 ║ 0 ║ 1 ║ ADAR ║
        ║ 0 ║ 1 ║ 0 ║ IAB ║
        ║ 0 ║ 1 ║ 1 ║ DTB ║
        ║ 1 ║ 0 ║ 0 ║ BAR ║
        ║ 1 ║ 0 ║ 1 ║ DW ║
        ║ 1 ║ 1 ║ 0 ║ DWS ║
        ║ 1 ║ 1 ║ 1 ║ INTAK ║
        ╚══════╩══════╩═════ ═╩═════════════════╝
 To use all the capabilities of the generator to create
sound pictures, it is enough to have only four signal combinations
fishing BDIR, BC1, BC2. This is achieved by connecting BC2 to the bus
supply +5V.
 ╔══════╦══════╦═════ ═╦═════════════════╗
        ║ BDIR ║ BC2 ║ BC1 ║ CP 1600 FUNCTION ║
        ╠══════╬══════╬═════ ═╬═════════════════╣
        ║ 0 ║ 1 ║ 0 ║ not active ║
        ║ 0 ║ 1 ║ 1 ║reading from PGZ ║
        ║ 1 ║ 1 ║ 0 ║ entry in PGZ ║
        ║ 1 ║ 1 ║ 1 ║ fix address ║
        ╚══════╩══════╩═════ ═╩═════════════════╝

Analog channels A, B, C (outputs) - Pins 4, 3, 38.

 Used to generate a composite audio signal with
double amplitude up to one volt. Are weekends
signals from the corresponding digital-to-analog converters
(DAC).

IOA7-IOAO (input/output) - Pins 14-21.
IOB7-IOBO (input/output) - Pins 14-21.

 They are parallel input/output ports. Used
for exchanging data with external devices connected to the con-
clocks IOA OR IOB, on the generator-processor bus. All conclusions
equipped with internal backup resistors, so in mode
input will read a normal high level.

TEST1 - Conclusion 39.
TEST2 - Conclusion 26.

 Designed for testing the generator and therefore in re-
It is not used in any other schemes. The peculiarity is that
these conclusions must always be free.

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