Dni-Pro #02 30 марта 2001

Железо

Anatomy ZX - LSI architecture parallel KP580BB55 (PART II).

                KR580VV55


                PART II


   For output operations control signal INTE A channel is 
carried out through PC6, and channel B - through PC2.




  By PA (7-0) <

  P PC (7,6) <> I / O

  5 PC5> IBFa

  8 PC4 o  INTRa

  In PB (7-0) <

  In PC2 o  IBFv

  5 PC0> INTRv


D7 D6 D5 D4 D 3 D2 D1 D0

1 0 1 1 1 / 0 1 1 X

                            Fig.4


    Figure 4 shows an example configuration
FDI in mode 1 and the corresponding control word input through 
the A, B, and in Figure 5 for output.




  By PA (7-0)>

  P PC7 o> OBFa

  5 PC6 o  I / O

  0 PC3 

  In PC2 o  OBFv

  5 PC0> INTRv


D7 D6 D5 D4 D 3 D2 D1 D0

1 0 1 0 1 0 1 0 X

                            Fig.5


    Not used to transmit control signals through PC6, PC7 (Fig. 
4) and PC4, PC5 (Fig. 5) can be pre-programmed for input (D3 = 
1) or output (D3 = 0). On Figure 6 shows the configuration 
option in the PPI Mode 1 for finding information on channel A

and input on channel B control word of this variant has the 
form "1010D311X", where D3 defines the operation of the lines 
PC5, PC4 on input or output.




  By PA (7-0)>

  P PC7 o> OBFa

  5 PC6 o  I / O

  0 PC3  IBFv

  5 PC0> INTRv

                             Fig.6


    Time diagrams of the PPI in Mode 1 at input and output data 
are shown in Figure 7 and 8. 


STB


IBF


INTR


RD


PA / PB



                             Fig.7


WR


OBF


INTR


ACK


PA / PB



                             Fig.8


    Mode 2 provides bidirectional
data transfer via the external A
device and vice versa. The exchange process is accompanied by 
five control signals fed on lines PC7-PC3. The remaining 11 
interface lines can be configured mode to 0 or 1.Raspredelenie 
signals interface lines and the control word

Mode 2 are shown in Figure 9.



  By PA (7-0) <>

  P PC3> INTRa

  5 PC4  IBFa

  0 PC6  OBFa

  In PB (7-0) <>

  5 PC (2-0) <>

  5


D7 D6 D5 D4 D3 D 2 D 1 D 0

Jan. 1 X X X 1 / 0 1 / 0 1 / 0

                            Fig.9


    D0 discharge in this configuration setting to determine the 
PPI input or output lines intrefeysnyh PC2, PC1 and PC0. 
Options control signals similar to those discussed above, the 
signals for mode 1. Control of the internal signal INTE for 
input operations carried out on the line PC4, and for output 
operations - through PC6. Timing diagram of the PPI mode 2

shown in Figure 10.


WR


OBF


INTR


ACK


STB


IBF


PA


RD



                             Fig.10


    Figure 11 shows one possible
options combine the modes of
FDI, in which channel A - pre-programmed
to Mode 2, and channel B - the output mode
1.



  By PA (7-0) <>

  P PC3> INTRa

  5 PC4  IBFa

  0 PC6  OBFa

  In PB (7-0)>

  5 PC2> OBFb

  5  INTRb


D7 D6 D5 D4 D3 D2 D1 D0

Jan. 1 X X X 1 0 X

                          Fig.11


    In modes 1 and 2 may conduct
monitoring the state of the external device and the PPI. 
Control is exercised reading word-channel state C at the 
command OUT. Format word-state shows Figure 12. For mode 1 I / 
O signals in discharges with definite numbers indicate for I / 
O operation on an interface lines of the channel C with the 
same numbers. For Mode 2, the values ​​of digits D2-D0 are 
determined only by the regime of group B. 

 Mode 1. Input

D7 D6 D5 D4 D3 D2 D1 D0

I / O I / O IBFa INTEa INTRa INTEv IBFv INTRv


       Group A Group B
<> <>

 Mode 1. Output

D7 D6 D5 D4 D3 D2 D1 D0

OBFa INTEa I / O I / O INTRa INTEv OBFv INTRv


       Group A Group B
<> <>

 Mode 2

D7 D6 D5 D4 D3 D2 D1 D0

OBFa INTEa IBFa INTEa INTRa X X X


       Group A Group B
<> <>


                             Fig.12


    A fragment program that implements the process of typing in 
a computer memory signal groups from N sensors with the help of 
FDI and the ADC can be following form:



          .....

          .....

          DI

          LD A, # BB

          OUT (# FF), A *

          LD HL, ADDR

          LD D, N
WAIT IN A, (# FE)

          AND # 80

          JR NZ, WAIT

          IN A, (# FD)

          LD (HL), A

          INC HL

          IN A, (# FE)

          AND 3

          LD (HL), A

          INC HL

          DEC D

          JR Z, EXIT

          LD A,% 00001100

          OUT (# FE), A

          INC A

          OUT (# FE), A

          JR WAIT
EXIT EI

          ....

*: For Speck ports naturally need

   pick up others.


    The program can be run at certain times on request timer 
interrupt that connect sensors to the ADC. After conversion, 
the signal of one from the sensor ADC generates control

tone, indicating the need for information storage and the 
ability to switch it to convert signal the next sensor. The 
program organizes a cycle for processing signals from all 
sensors of the system, write to infor mation from the ADC in 
the selection memory using the bit-mode control channel C 
generates a signal switching of "ADC to process the information 
another sensor. 

    The program involves the use of
system 10-bit ADC, 8 LSBs are entered into the memory cell via
B, and two senior level - along the lines of PC1,
PC0 channel C to the next memory cell. By
PC7 line receives a signal of readiness from
ADC, and reset and setting discharge PC6 is used for signal 
switching, "ADC. Control word specifies the following 
configuration: PPI: Channel B - input mode 0; line PC1, PC0 
channel C - commissioning Mode 0, channel A is used to, but

configured to input in mode 1 to
PC7 use the line for input and further analysis of tone and ADC
manage the discharge-level installation PC6.
Channel C in the program has an address # FE; channel
B - FD; control register - # FE; starting address of memory to 
store the sensor signals assigned to the symbolic name ADDR.



    Basic electrical parameters of circuit KR580VV55 the 
following: 

Output voltage logic zero, B
.............................<= 0.4

The output voltage of the logical units in
.............................>= 2.4

Current consumption from the power source, mA
.............................<= 60

Leakage current channels A, B, C, D at nevybranom
mode, uA ..................- 100 .. 100

Leakage current upralyayuschih inputs, uA
.............................- 10, .., 10


   Well, now you can do to VV55


        KEMSTON MOUSE

 Party details

 1 Party

 2 Parties

 Scheme unload in the text and look at

       BV or any editor.


                                        Ya 15

                      XS 2 C CT2

                                        Yb 10 June 1922

                                   Xa UD 1 PB4 PIO

                      1 Xa 11 May 1923

                                   Xb oCI 2 PB5

                      Xb 2 15 7 1 14 24 26

  XS 1 Ya C CT2 COo PE 4 PB6 Ucc +5 V

                      Ya 3 10 9 2 25 July

                                  Yb UD R D3 8 PB7 GND
A2 D7 4 Yb 5 June 1918

                                  Km oCI a PB0
A3 D6 5 Km 11 September 19 VA0

                                  Ki 2 PB1 A0
A4 D5 6 Ki 14 January 1920 8 VA1

                                 +5 V PE 4 PB2 A1
A5 D4 7 Vcc 9 February 1915 21 35 VRES

                                 GND R D1 8 C CT2 PB3 RES
A6 D3 8 GND Xa June 10 1940 June VCS

                                  Kr UD 1 PA4 CSo
A7 D2 9 Kr Xb May 11 1939 36 R4 +5 V

                                                                
            oCI 2 PA5 WRo __ A8 D1 15 7 1 14 38 5 RD


                                                  C CT2 COo PE 
4 PA6 RDo A9 D0 A5 1 15 10 9 2 37 34 D0


    __ A0 DC 0 o VD R D4 8 PA7 D0
A14 RD 2 May 4 June 1933 D1

         VA0 A1 1 o oCI a PA0 D1
A21 A10 3 Mar. 11, 1932 D2

                      A2 2 o 2 PA1 D2
A23 A8 1 14 February 1931 D3

                 +5 V 3 o PE 4 PA2 D3
A26 A5 9 1 Feb. 1930 D4

                             4 o R D2 8 PA3 D4
B1 GND IORQ 4 Kr R1, 2,3 14 29 D5

                     oE1 5 o PC0 D5
B3 +5 V WR 5 C1 R7 * Ki 15 28 D6

                     oE2 6 o PC1 D6
B10 GND DOS 6 +5 V + Km 16 27 D7

                      E3 D6 7 o PC2 D5 D7
B13 WR VCS VRES +5 V

B22 IORQ C2 VA1

                                             By D1 ... D4 - 
K561IE11: B27 DOS A8 / +5 D5 - KR580VV55A:


                                                  R6 D6 - 
K555ID7 (KR1533ID7) B29 +5 V R5 B E R1 ... R6 - 1 kohm: UT1 - 
KT315 

                                       UT1 R7 - 10 k: C2 -3,3 pF
B31 GND C1 - 10.0 pF + 16B


NOTE: CONNECTOR XS2 MEETS SUCH STANDARDS AS (COMMODORE-AMIGA, 
ATARI-ST, CREATE SOFT MOUSE) 

            AND MOUSE FROM THEM FIT.