Nicron #22 27 февраля 1997

Железо

Iron - an overview of the microprocessor Zilog Z380, continued.

                          MPU Z380

[Continued. The beginning of a cycle of publications in room 7].

(C) WLODEK BLACK

            Upper memory

The area of ​​upper memory is determined by the final address 
and 00FFFFFFH the starting address given by the registers and 
UMCSR0 UMCSR1 similar similar to the lower memory the only 
difference is that bit-check on getting the addresses in the 
range of upper memory produced by the logic "or": it is enough 
to at least one specified category of address bus carry logic 
1, the signal sampling of the upper memory / UMCS activated 
(subject to permission of the sample at all). 

            Register UMCSR0:

     MA15 MA14 MA13 MA12 0 0 0 ERF



            Register UMCSR1:

     MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16


Bits MA23 ... MA12 determine the level address bus, which should
checked for logic 1 for issuing a signal / UMCS.
ERF bit when installing a logic 1 enables the regeneration of 
upper memory. 

            Average memory

Under the scheme 1 (see NICRON 20), the user can specify the 
base address and the total size of the average memory, which 
will automatically divide into 4 equal area by the CPSU in 
attempts to appeal to it. The range of these areas will be 
determined by 4 possible combinations of bits A14 and A15 of 
the full address. Under the scheme 2 (ibid.), the average 
memory is placed between the lower and upper memory and defines 
the boundaries of the latter. 

            Register MSMER:

     ENLM ENUM ENM1 ENM2 - - - SR

       1 1 0 0 0 <-After
                             Reset

The choice of scheme 1 or 2 for the organization of secondary 
memory, as well as permission to sample the upper or (and) low 
memory, as well as permit the formation of temporary delays in 
cycles of treatment to these memory regions is performed using 
the general ledger permit memory access (MSMER). Logic 1 in the 
corresponding bits authorizes the following actions:


ENLM - sampling the bottom of memory formation and time delays;
ENUM - a sample of upper memory and the formation of the delays;
ENM1 - the inclusion of the 1 st circuit secondary memory and 
the formation times        GOVERNMENTAL delay;

ENM2 - the inclusion of the 2 nd circuit secondary memory and 
the formation times        GOVERNMENTAL delay;

SR - for 0 - a global ban on the Communist Party and the 
blocking 

       making all of its signals.

When ENM1 = 1 and ENM2 = 1 signal / MCS0 will be generated for 
any accessing secondary memory, and signals / MCS1 .. 3 - Logic.

When ENM1 = 0 and ENM = 0 the term "memory medium" is missing.

            Register MMCSR0:

     MA15 MA14 - - ERF3 ERF2 ERF1 ERF0



            Register MMCSR1:

     MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16



            Register MMCSR2:

     BA15 BA14 - - - - - -



            Register MMCSR3:

     BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16


Level BA23 ... BA14 sets the base address bits, and bits
MA23 ... MA14 show which bits address bus of the processor
must be analyzed to identify the treatment of secondary memory. 
The logic here is: if any bit of MA is 1, then corresponding 
address bit is compared with the corresponding bit of the 
number of bits BA, and so on for the entire chain of bits 23 
... 14. By overall results comparing the decision on fielding

one of the signals / MCS0.../MCS3. In the complete absence of 
matches address bits = bits BA decided to failure to select 
middle memory.

Level ERF determine the appropriate resolution of regeneration
areal average RAM.
When working on the scheme 2 bits MA and BA do not carry useful 
information, using only the discharge ERF0 Register MMCSR0 to 
determine permit recovery of all secondary memory. 

[To be continued].

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