Nicron #18
31 января 1997 |
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Iron - an overview of the microprocessor Zilog Z380, continued.
MPU Z380 [Continued. Previous publications - in numbers 17,16,15,14,12, 11,10,9,8,7] (C) WLODEK BLACK Register of the internal space I / O devices (EP UVV) Register Address Mnemonic in the EP UVV Register-0 chip-select lower memory chip LMCS0 00000000H Register-1 chip-select lower memory chip LMCS1 00000001H Register-0 chip-select top memory chip UMCS0 00000002H Register-1 chip-select top memory chip UMCS1 00000003H Register-0 chip-select secondary memory chips MMCS0 00000004H Register-1 chip-select secondary memory chips MMCS1 00000005H Register-2 chip-select secondary memory chips MMCS2 00000006H Register-3 chip-select secondary memory chips MMCS3 00000007H Control register ticks wait (WAIT) for the lower Memory LMWR 00000008H Control register ticks expectations for the upper memory UMWR 00000009H Register-0 control ticks expectations for the average memory MMWR0 0000000AH Register-1 control ticks expectations for the average memory MMWR1 0000000BH Register-2 control ticks expectations for the average memory MMWR2 0000000CH Register-3 control ticks expectations for the average memory MMWR3 0000000DH Control register ticks waiting for operations I / O IOWR 0000000EH Control register ticks waiting for the regeneration cycle Memory RFWR 0000000FH Main Control Register resolution of the choice of crystals memory chips MSMER 00000010H Register-0 bus control in the I / O IOCR0 00000011H Register-1 bus control in the I / O IOCR1 00000012H Register-0 refresh memory RFSHR0 00000013H Register-1 memory regeneration RFSHR1 00000014H Register-2 regeneration memory RFSHR2 00000015H Register mode control cost-stop SMCR 00000016H Interrupt enable register IER 00000017H Register a common base of interrupt vectors from inputs / INT1, / INT2 and / INT3 AVBR 00000018H Register flags on the facts interruptions on errors in the code Team TRPBK 00000019H [To be continued].
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