ZXNet эхоконференция «hardware.zx»

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MODULE SC15_3
"Created by JED2AHDL ABEL 6.00 on Fri Feb 23 00:23:45 19:7

TITLE 'TURBO 15.3'

SC15_3 device 'ep220';

"Pin and Node Declarations
CLK_7MHZ, IORQ_, WR_EN, RAM_ PIN 1, 2, 3, 4;
INT, TRB_IN, BORDER_, M1_ PIN 5, 6, 7, 8;
H0, H1, H1M PIN 9,11,12;
Pin13, WR_BUFF, RAS_, TRB PIN 13,14,15,16;
WE, CLK_CPU, WAIT_ PIN 17,18,19;

Pin13,WE ISTYPE 'Neg';
H1M,WR_BUFF,CLK_CPU,WAIT_ ISTYPE 'Com';
Pin13,RAS_,TRB,WE ISTYPE 'Reg_D';
H1M,Pin13,WR_BUFF,RAS_,TRB,WE,CLK_CPU,WAIT_ ISTYPE 'Buffer';

X,K,Z,C,P,U,D = .X.,.K.,.Z.,.C.,.P.,.U.,.D.;

EQUATIONS

H1M = (H1 & !TRB.Q
#BORDER_ & H1 & TRB.Q);
H1M.C = CLK_7MHZ;
H1M.OE = (1);

Pin13.D = !(!IORQ_ & Pin13.Q);
Pin13.C = CLK_7MHZ;
Pin13.OE = (1);

WR_BUFF = (!BORDER_ & H0 & TRB.Q
# H0 & !H1);
WR_BUFF.C = CLK_7MHZ;
WR_BUFF.OE = (1);

RAS_.D = (H0);
RAS_.C = CLK_7MHZ;
RAS_.OE = (1);

TRB.D = (!WR_EN & RAM_ & INT & !TRB_IN & !H1 & !RAS_.Q
# WR_EN & TRB.Q
# H1 & TRB.Q
# RAS_.Q & TRB.Q
# !RAM_ & TRB.Q );
TRB.C = CLK_7MHZ;
TRB.OE = (1);

WE.D = !(WR_EN & !BORDER_ & RAS_.Q & TRB.Q
# WR_EN & !H1 & RAS_.Q);
WE.C = CLK_7MHZ;
WE.OE = (1);

CLK_CPU = (CLK_7MHZ & TRB.Q
# RAS_.Q & !TRB.Q);
CLK_CPU.C = CLK_7MHZ;
CLK_CPU.OE = (1);

WAIT_ = (!WR_EN & RAM_ & Pin13.Q
# !BORDER_ & Pin13.Q & !RAS_.Q
# !H1 & Pin13.Q & !RAS_.Q
# !TRB.Q);
WAIT_.C = CLK_7MHZ;
WAIT_.OE = (1);

END

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