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║Section: Do it yourself; ║
║Article: Application of micro. K155 series; ║
║Music:Dreamer; ║
║Text: Vorozhkin Alexander. ║
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Microcircuit K155IR15 (Fig. 1) represents
is a four-bit register with
possibility of switching outputs to
juice impedance state.Consumed
its current does not exceed 72 mA, maximum
clock frequency
equal to 15 MHz.
Information received at inputs D1-D4
written to register flip-flops by
front of the positive clock pulse
sa at input C. When exposed to the same
pulse to input R they are set
to the zero state. The register has two
peer input write permission
EWR.Presence of level 1 on any of them
prohibits writing to triggers. Signals on
inputs EWR and D1-D4 can change with
any level (0 or 1) at input C, important
only their state immediately before
front of a positive impulse on this
input. The microcircuit also has two equal
equal to input EZ. At level 1 at any of
them, the register outputs switch to high
juice impedance state, and work
microcircuits for other inputs (recording and
zeroing) is not violated.
Basicsthe purpose of the register is to record,
storage and transmission of information. For use
measure in Fig. 2 shows a diagram of the device
VA for simultaneous recording of four
bit information from sources
<> and <> on edge
clock pulse at the <> input and
alternately transmitting it to the outputs via
signals <> and <>.
Availability of two write permission inputs
EWR and converting outputs to high impedance
EZ state makes it easy to organize
call matrix control a large number
scrap microcircuits. For example, two microcircuits
K155ID4 can control (one horizontally
umbrellas, the other vertically) with a matrix of
64 registers K155ИР15 on inputs EZ.В re-
As a result, simultaneous
recording and storing 256 bits of information
and serial transmission of it in 4 bits
in the required order. Managing the matrix
registers at the EWR inputs, you can sequentially
it is important to record information from
personal sources and in parallel transmitted
use it if the outputs of the microcircuits are not combined
nena.
Chip K155IR17 (see Fig. 1) - special
cial register intended for
construction of analog-to-digital converters
controllers (ADCs) operating on the principle
successive approximation, with number
12 discharges. The current consumed by it is notpre-
exceeds 124 mA, the maximum frequency follows
clock pulses - 15 MHz.
The register has a C input for negative
clock pulses (register flip-flops
switch according to their decline), input D for
signals of stored information, inputs
ERD conversion resolution and reset. S.
The operation of the microcircuit is illustrated by time-
diagrams of signals at the inputs and outputs
dah, shown in Fig. 3. At level 0
at the ERD and S inputs according to the decline of the next
negative clock pulse is converted
the formation of P also produces level 1.Ta-
Some register state is retained until
as long as S is present at the input
level 0.
After level 1 arrives at input S
decline of the first clock pulse (1)
writes to the register trigger from the output -
mi 12' and 12 information from input D (has
value level before clock fall
pulse), sets output 11
level 0, and at outputs 1-10 and P remains
level 1. Since in our case the input
D affects level 1, then output 12
the same level appears. The decline follows
blowing clock pulse (2) recording
provides information from input D (also level
1) into a trigger with output 11 and set
at output 10 level 0, etc. Thus
way at the register outputs alternately
level 0 appears and then information
from input D.
After pulse 12 writesin-
formation into a trigger with output 1, output
P level 0 appears and the state of re-
hysteria is fixed before the appearance of such
the same level at input S. If the last
connect with output P, then in turn -
clock pulse (13) register
will be established in the initial state (ana-
logical to impulse 0) and will repeat further
the cycle of work described above with a period
13 bars.
If level 1 is supplied to the ERD input,
outputs 1-12,P the same level appears
vein that does not change from signals to
other inputs. By connecting output P to one
microcircuits with an ERD input are different, as yet -
shown in Fig. 4, registers can be built
at 24,36,48, etc. discharges. Such re-
hysters work similarly to one micro-
circuit, and when connecting output P to the last
with combined inputs S - cyclically with
period respectively 25,37,49, etc.
clock cycles. The chip can also be used
like a register with fewer bits
(11-1), if input S is connected to the corresponding
current output (1-11).
When a constant level is applied to input D
Register 1 works as a counter-decipher-
torus, the outputs of which alternately
time period of clock pulses appearing
Level 0 is displayed. Conversion factor
such a counter is equal to 13 if the input S is
is the same as the output P, but may be less
above (2-12) if this input is connected to
relevantoutput (1-11). If
level 0 is constantly applied to input D, then
on the decline of each clock pulse level
thread 1 at the next of the exits 11-1 shift
is set to level 0 and remains so until
the end of the cycle, and at the output 12 is present
constant level 0. Cycle duration
the same as in the previous case, maybe
be from 2 to 13 clock periods
pulses.
The diagram of a possible ADC option is shown
on in fig. 5.To outputs 1-12 of the microcircuit
DD1 is connected to a digital-to-analog converter
caller (DAC) DA1, which has 12 - the oldest
Lowest digit, input 1 - low-order. Comparator
DA2 compares the output voltage of the DAC and
convertible input DAC and comparator
can be of many different types, for example,
you can use K594PA1 and K554CA3
accordingly.
Clock pulse 0 (see Fig. 13) is set
resets register DD1 to its original state,
and the inputs of the DAC DA1 receive signals from
yes 011...1. At its output a level appears
value equal to half the maximum pre-
the voltage generated by the DAC, and a comparator
DA2 compares this level with the input level.
If the latter turns out to be larger (see.
diagram U/Uin.max), at the output of the comparator
torus level 1 arises. Clock im-
pulse (1) it is recorded in the trigger
with output 12 and saved until the end
conversion (with a lower input voltage
when dressing up, the level will be recorded in this trigger
ven 0).At the end of clock pulse 1 on
output 11 of register DD1 appears
line 0, and a level appears at the DD1 inputs
0, and the DAC inputs receive input signals
yes 1011...1.Now input voltage
compared to level 3/4 (1/2+1/4)
converted DAC. If it is larger and
this value (see Fig. 3), into a trigger with
output 11 also records level 1
(otherwise - 0) by the next clock
pulse (2), and the DAC is affected by the signal
code numbers 11011...1. In this case, the input is
The new voltage is compared with the level
7/8 (1/2+1/4+1/8) from the maximum and,
if it becomes smaller (as in
Fig. 3), into a trigger with an output of 10 records -
level 0 is set, and the comparison level is
decreases by 1/16, etc.
After pulse 12 at outputs 12-1 re-
hyster contains binary signals
twelve-bit parallel code
(for our case 110101...01), and the level
line 0 at output P signals
completion of the transformation and maybe
used for rewriting signals
generated code into the storage register.
During conversion at output D0
register appears delayed by one
clock period information from
input D, i.e. serial signals
input voltage code. When connecting
output P with input S (see Fig. 15) operation
The ADC becomes cyclic with a period of 13clock cycles. The ADC capacity can be reduced
shen (when using any
from outputs 1-11) or increased (if connected
connecting registers according to the diagram in Fig. 14 and
connecting a DAC with the corresponding number
inputs).
The K155IR17 chip can be used
also in devices manufactured by others
operations based on the sequential principle
approximation. For example, by connecting to the re-
gistru digital code multiplier, you can
build a device that extracts quad-
military roots. At the same time, the signals of the initial
register states in code 011...1 read
are hidden by a trial value, which is digital
the first multiplier is squared, and
then it is compared by a digital comparator
with the code of the number from which it is extracted
root.Then the device operates analogously
gically ADC, and at its outputs you get
square root code signals.Same
in this way the device can divide codes or
determine the code of the reciprocal number.
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