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ZX Pilot #31
20 февраля 1999 |
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VideoPort - The recommendations of assembling, tuning and programming of video (digitizer).
B AND D E O P O R T (Part I)
(C) AlphA Studio
This article is recruited by numerous
request editor ZX-PILOT'a
VEL'a. Pounded on the keys in the IS-EDITOR'e
Igor of AlphA Studio.
In this article, will be discussed on the device
referred to as "VideoPort, developed Manilov AP and published
in the ZX-FORUM'e # 2. It is possible that not all willing to
collect "video port" is available this book, however, and
recruited The following article. It will also be given some
recommendations for the assembly and adjustment not only
from the author, but also from me.
(C) Manilow, AP Moscow, 1994
Image input device, encoded video signal, a ZX-compatible
computers with the software.
INTRODUCTION.
Have you tried to draw a picture with an image-editing ART
STUDIO? If the majority nothing good happened, it's not because
poor ZX machine or ART STUDIO done stupid. This
the result of natural, since the ability to draw all men have
not. But sometimes you want in your program
put a good picture. Such a possibility you can get equipping its
ZX-Spectrum device "VideoPort.
(The examples are not far to seek -
THE PUZZLE game and others use the scanned image, which does not
spoil these games ).
The idea of development has been derived by the author
from the publication ZX-REVIEW-1991 (p.121), in
which reported the existence of the device "Videoface" firm
"DATA-SCIP". Not without knowledge of the principles of
building "Videoface", author called his device "VideoPort. Name
comes from the fact that the device plays the role of an input
port, but not for digital signals, and for the video.
"VideoPort" is connected to the video output TV, camcorder,
VCR. Place the device in the system shown in Fig. 1.
TV
VIDEOPORT POWER
DRIVE ZX-SPECTRUM
DISPLAY
Fig. 1.
To PC "VideoPort" connects
buffered by bus to external devices. Powered device can be
realized from the power supply drives (+12 V, +5 v).
Under the direction of the program is loaded
in ZX, picture frame is copied into RAM
device, then read in the ZX-Spectrum,
transcoded to a format screen is displayed. Complete cycle of
moving images on the screen - about one- second. The resulting
image can be flushed to disk.
Hardware Specifications.
- Input resistance
by videvhodu. . . . . . . . . . 100 Ohm
- Amplitude of the input signal. . . 0.5-1 IN
- Sampling frequency. . . . . 7 MHz
- Number of rows stored in RAM. 312
- Supply voltage. . . . . . . +12, +5 V
- Current consumption of the circuit 12 B. . 40 mA
the chain of +5. . 320 mA
- You can manually install
Contrast and white balance;
- Connects to the ZX-Spectrum through the buffer
ized bus peripherals.
Software made by the author, has three variants: for the
system ISDOS, for TR-DOS system and recorder. (The following
program is only for the system TR-DOS ).
FUNCTIONAL SCHEME OF THE DEVICE.
The principle of operation of the device "VideoPort"
explains the functional scheme of Fig. 2.
We list the functional devices
indication of their purpose:
MATCHING SYSTEM - is intended
to harmonize the external circuit.
DEVICE ALLOCATION Clock -
provides a selection of video
vertical sync (SI) and human
clock (CI). Provides noise reduction and issues of SI and CI,
with a stable duration and amplitude.
Comparator - ensures the formation of
the level of the video and compare with a given
level. Has a manual level control
Video and level of response komporatora.
Shaper clock - determine the sampling rate video
and provides the synchronization of shift register and control
circuits of RAM.
SCHEME OF RAM - generates address
RAM read and write signals in accordance with the mode of
operation.
REGISTER DATA - used to transfer
data from RAM to the data bus ZX-Spectrum.
Control Register - for
transmission of control signals from the computer to the
control of RAM.
The status register - is used to transfer
status of the device into your computer.
DECODER - provides decryption
Signal system bus ZX-Spectrum at
accessing the data registers, control and
state.
The device operates in two modes:
- Recording mode in the RAM, the computer is initiated;
- Read mode of RAM, is under the control of
computer.
Standby mode occurs at the end
any major mode. Tag Mode
expectations - a high level signal READY
at a high level signal MODE from the computer.
The matching video input
device
Device
allocation
The video signal sync
Comparator
Shift shaper
Shift clock
signals
Registry Fixing
Reading Gate CI
SI
Address
Recording Scheme
RAM Management
Reading RAM
Data by reading Reset
Invoice address line
byte mode
Register Register
Data Management
DATA CSD CSC Ready
CSS
Decoder Register
state
/ IORQ / RD / WR A0 A1 A4 DATA DATA
System diagram of ZX-Spectrum
Figure 2.
Consider the recording mode to RAM. For clarity, an
explanation of the device Fig. 3 shows a sequence diagram of
signals obaznachennyh on a functional circuit.
Prior to time t0 signal levels indicated in the sequence
diagram, block the entry RAM. The device is in standby mode. At
the time t0, the command ZX-Spectrum, transmitted via the
control register, the signal MODE is set to "0". At this signal
the control circuit memory goes in a wait state pulse staffing
(CI).
Upon receipt of the CI at the time t1 the control circuit
resets the RAM signal "READY". This moment corresponds to the
start recording images in RAM. The computer received via
register state signal "READY", the corresponding
logicheskuomu zero, sets the level
signal "Mode" in the unit and goes into
state of waiting the end of the recording to RAM. This
event occurs within 20 ms of t1 in
time tc. From the moment t1 of all processes in the device
controls the control circuit of RAM.
Mode
t0 t1
Ready
20 ms
CI tc
SI
Gate 1 2 3 4 5 6 7 8 1 2 3 Frequency
7 MHz
. . . . . . . . .
Shift
. . . . . . . .
Fixation
. . . . . . . . . . . . . . . . . .
Each of SR increases the RAM to address the values, multiple
of 64. Each pulse increases FIXATION hell res RAM 1.
Fig. 3.
At the time t1 RAM address reset to 0.
Begin the transformation into video
sequence of bytes. Shaper
clock synchronized vertical sync. Output signals
shaper signals "GATE" and "SHIFT"
shifted relative to each other, that
ensures the consistency of the shift register and control
circuits of RAM.
Signal Offset fed to the shift
Register, provides storage level
at the output of the comparator in the shift register. On every
eighth signal "STROBE" RAM control circuit generates signals
"READING", "fixing" of the shift register and
"Record" of RAM. In addition, the control circuit increases the
RAM address RAM in the unit. Thus there is a write to RAM
line image.
When you receive the next row
clock on the control scheme of RAM
being installed RAM address corresponding to the first byte of
a new line. Next everything is the same as for the previous
line. Thus, line by line,
in RAM, there is a copy of the images in this
copy bits with a value of 1 corresponds to
dark areas, and the value
0 - highlights.
If you receive a regular staff
pulse on the control circuit memory process
RAM recording is terminated, the signal "READY"
installed in the unit. Device VideoPort "goes into standby mode
commands from the computer. In this mode, the device
may be up to removing the food, for
This copy of the images in memory will be preserved.
Consider a read mode of RAM. For clarity, in Fig. 4 shows
the sequence diagram signals in the read mode of RAM.
Mode
Ready
Reset Address
Expense lines to address setting
January 2 k "k" line
. .
Account byte address setting for
February 1 m "m"
. . bytes
CSD (Select Data register)
Reading from RAM Register
Management
Start reading mode RAM
Transfer data byte in the ZX
(B Compliant "k" line
and "m" column of the screen).
Fig. 4.
This mode is completely under computer control. All signals
are sent through the control register. To begin the process of
reading the RAM produces a signal "RESET ADDRESSES. "As a
result, the control circuit of RAM set the address to zero.
Before reading, if you want, you can set the line number and
number of bytes in a row. It's enough to apply for a RAM
control circuit corresponding number of signals "SCORE LINES"
and "COUNT BYTES. You can then read
the contents of bytes of RAM, which should give a signal "read"
through the control register and receive data from the data
register. Thus, it can read data from RAM
starting with any string and any byte in
line. This allows you to select the desired part
from the entire video frame for conversion to
size standard picture ZX-Spectrum.
The entire exchange of commands and data between
device and the ZX-Spectrum by
through registers. Revitalization of the registers is the
decoder that analyzes signals to the system bus ZX-Spectrum and
issue appropriate signals to the sampling registers commands
IN, OUT with the relevant port address.
The description of the functional diagram
ends.
B AND D E O P O R T (Part II)
(C) AlphA Studio
Schematic diagram
Device VideoPort.
D1
January 10 A0 RAM D0 November 1917
September 2 A1 D1 18 December
August 3 A2 D2 13 19
July 4 15 20 A3 D3
May 6 A4 D4 16 21
June 5 A5 D5 17 22
July 4 A6 D6 18 23
August 3 A7 D7 19 24
September 1925 A8
October 1924 A9
November 1921 A10
December 1923 A11
February 13 A12
14 20/CS1
C 26 CS2
15 27/WR 5B 14 A
16 22/CEO 0B 28 D
D2
RAM
25 20/CS1
D3
RAM
26 20/CS1
D4 D6
37 1 / R C 0 14 January 1935 1 / R C 0 14 July
38 2 / C T 1 13 2 36 2 / C T 1 13 8
C 9 L0 2 12 3 C 9 L0 2 September 12
March 1911 7 CT on April 7 CT 11 March 1910
10 CR P2 October 27, 1910 CR P2 October 1929
D10.1 D10.2
27 1 1 / 2 28 29 3 1 / 4 30
D5 D7
37 1 / R C 0 14 May 1935 1 / R C 0 14 Nov.
February 28 / C T January 1913 6 Feb. 30 / C T 13 January 1912
C 9/L0 C 9/L0 12 February 1913
7 CT 7 CT 11 March 1933
10 CR 10 CR P2 15 31
D8.1 D9
/ S T Q May 1934 33 1 A0 D 0 / 15 14
32 3 / C 34 2 A1 C 1 / 14 25
C 2 D D 3 A2 2 / 13 26
35 1 R C 6 E1
D 4/E2
D10.5 5/E3
31 11 1 / 10 32
D18 D19
48 11 / C R Q0 April 3 D0 R 0 February 1917
D 23 S1 G Q1 June 4 D1 G 1 May 1918
C 1 S0 Q2 August 7 D2 6 February 1919
58 2 DR Q3 August 10 D3 9 March 1920
Q4 14 13 D4 12 April 1921
Q5 16 14 D5 15 June 1922
Q6 18 17 D6 16 July 1923
C 13 / R Q7 20 18 D7 19 August 1924
1/E0
50 11 LD
44
D11.1 D10.3
39 * 1 '3 5 1 / 6 35
41 2
D11.2
VD1
40 4 '6 * 36
45 5 R1
* D
D11.3 D10.4
VD2
9 '8 * 9 1 / 8 37
42 10
D11.4
D17.1 VD3
40 13 '11 * 38
1954 / S T Q 5 39 44 12
55 D
56 / C Q / June 1940 D12.1
VD4
39 1 '3 *
D17.2 43 2
R2
/ S T Q 9
40 12 D D15.3 D14.4
44 11 / C Q /
9 '8 * 9 1 / 8 50
D16 1910
D14.5
47 1 / R C 0
46 2 / C T 1 13 11 1 / 10 15
C 9/L0 February 1912
7 CT March 11
10 CR P2 D15.4
49 13 '11
Q1 1912
R3 R4
*
D13.1 D13.2 D13.3
C1
1 1 / 2 * * 3 1 / 4 * 5 1 / 6
VD5
D13.4
D8.2
45 9 1 / 8 *
12 D T Q
D14.1 11 / C
* 10 / S Q / 8 * 46
46 1 1 / 2
vD6 R5
* * A
D15.1 D14.2
VD7
1 '3 * 3 1 / 4 * 47
2
44
D14.3 D15.2
49 * 5 1 / 6 4 'June 1948
5
B *
58 R28
A * *
R33 R26
R23 C17 *
C15 VT1 + R34 VT2
+ / VT3 * * /
59 * * R35 / *
* R30
R37 R32
R24 R25 R
R31 1927
D * * * * * * * *
C15 * + R29
59
57
45
B C13 C14
C11 R16 +
*
2 4 6 12
C2 14 13 C12
D * *
16 D24 R
* 15 20
*
R8 R22
8 3 5 11 1 9 * C7 10
56 * C4 C5 C6 + R15 *
R10 * * * * R
45 * R12 * * 19
* C10
R9 VD10 R14 *
D C8 * *
R13 R18
R11
*
C9 R17
D B D D 57 D
D21 D22
D0 R 39 3 0 2 1 1 3 D0 R 0 February 1941
G May 1 2 2 4 D1 G 1 May 1942
Feb. 6 3 3 7 D2 6 February 1943
March 9 4 4 8 D3 9 March 1954
April 12 May 5, 1913 D4 12 April 1916
May 15 June 6, 1914 D5 15 May 1955
June 1916 7 July 1917 D6
July 19 August 8, 1918 D7 A
52 1/E0 1/E0 R7
C 11 LD 11 LD
C
D20 1953
D
March 17 D0 R 0 2 1 C
April 18 D1 G 1 5 2 D23
July 19 D2 2 6 3
August 20 D3 3 9 4 9 1 A0 D 0 / 15 51
21 13 D4 12 April 5 10 2 A1 C 1 / 14 52
22 14 D5 May 15 6 11 3 A2 2 /
23 17 D6 16 June 6 July E1 3 / 12
24 18 D7 7 19 August, 1912 4/E2
51 13 * 5/E3 1/E0
C 11 LD VD8
D 15 D13.6
13 1 / 12 53
1 D0 VD9 R6
D1 2 14 * A
3 D2 A0 9
4 D3 A1 10 59 VIDEO
5 D4 A4 11 Rdop
6 D5 / IORQ 12 +12 V 8
7 D6 / WR 13 B + +5 V * * * A
8 D7 / RD 14 +
15 General Cdop
D 0V * * * D
C18 C19-C41
Fig. 5.
The list of elements used.
D1, D2, D3 - K537RU17 R18, R20 - 82 ohms
D4, D5, D6 R19 - 12 ohms
D7, D16 - K555IE10 R23 - 22 ohms
D8, D17 - K555TM2 R24, R27 - 10 k
D9, D23 - K555ID7 R26 - 47 kohm
D10, D13, D14 - K555LN1 R28 - 820 ohms
D11, D12, D15 - K555LI1 R29 - 270 ohms
D18 - K155IR13 R30, R37 - 120 ohms
D19, D20, D21 R31 per. - 3.3 kOhm
D22 - K555IR22 R32 per. - 1.5 kOhm
D24 - K174HA11 R33 - 2.2 kohm
R34, R36 - 3 kOhm
VT1, VT2, VT3 - KT315 Rdop - 220 ohms
VD1-VD9 - KD522
VD10 - AL307 C1, C5 - 0.1 uF
C2 - 4.7 nF
R1, R2, R5, R6, C4, C8,
R7, R21, R25, C10, C14 - 0.22mkF
R35 - 5.1 kohm C6, C18 - 100 uF
R3, R4 - 680 ohms C7 - 6.8 nF
R8 - 1.6 ohms C9 - 100 pF
R9 - 200 ohms C11 - 47 nF
R10 - 510 ohms C12 - 10 nF
R11, R16 - 27 ohms C13, C15,
R12 - 33 kohm C15 *,
R13 - 2.2 megohms C16, C17 - 4.7 uF
R14 - 1.5 kohm C19-C41 - 150 nF
R15 - 1.8 megohms Cdop - 20 uF
Tune my R17. - 4.7 kOhm
R22 - 6.8 k Q1 - 14 MHz
Note: C19-C41 - ceramic capacitors mounted on the circuit +5
V, one for each body of the chip.
Just want to make some clarifications
on the design. Since the scheme
represented by pseudo-graphic, then
the following notation:
/ - Inversion;
* - The connection of conductors;
- Bus.
In transistors: Collector - on top
circuit output; emitter - the bottom.
To save space, chip D2,
D3 (K573RU17) are shown conditionally. All conclusions
These ICs are connected to similar pins D1, with the exception
of the signal / CS1 (vyv. 20). (Note I / ASt).
Description of the schematic diagram in Fig. 5, is based on
disclosure devices shown in the functional
scheme. Matching device is made on
transistors VT1, VT2. Cascade on VT1 -
emitter follower, which provides
harmonization of the line video transmission
internal devices VIDEOPORT'a. Cascade on VT2 inverts the video
signal that necessary for the proper operation of the device
isolation clock, which built on a chip D24. To install
Horizontal Frequency is provided
trimming potentiometer R17. To limit the amplitude of the row
pulse is chain R9, VD10, R10. VD10 LED indicates the presence
of vertical sync. D24 circuit is sensitive to deviations
resistance and capacitance values from those contained in the
annex to the concept.
The comparator is built on the transistor VT3.
Provides control of contrast and R31
balance control of black / white - R32.
Shaper clock built
on logic chips. Basis shaper - stabilized crystal oscillator in
the D13.1 and D13.2. The frequency of the quartz 14 MHz.
Synchronizing the shaper of SI through the element D13.4. D8.2
provides a trigger signal conditioning GATE. SHIFT signal is
formed on D14.1, D14.3, D15.2. RAM is built on three chips D1,
D2 and D3. Applied circuits - is a static RAM 8K each. The
control circuit consists of RAM as if from multiple sites.
Knot formation of memory addresses and the signal
sampling circuits includes counters D4, D5, D6, D7, logic
elements D10.1, D10.2, D10.5, D8.1 trigger and decode D9. A
control unit counters provides management, depending on the
mode of operation. Built this node on the logical elements of
D10.3, D10.4, D11.1-D11.4, D12.1, trigger D17.1. Node
READING signal shift register and the signal recorded in the
RAM is built on logic elements D15.1, D14.2, D15.3,
D15.4, D14.4, D14.5, D16, and a trigger counter D17.2. Shift
register is built on chips: D18 - shift register, D19
- Buffer register. The status register is built on a chip D21.
Control register is built on the D22. Register data - on D20.
The decoder is built on chips D23, D13.6.
By the ZX-Spectrum "VideoPort" connects
buffered by bus to external devices.
B AND D E O P O R T (Part III)
(C) AlphA Studio
The arrangement FEES
Devices VideoPort.
Recommendations for missile
devices on the board can be reduced to a few:
- Functional units should be placed compactly;
- Nodes are directly connected with the video signal must be
placed as far as possible away from the generator;
- Adjusting elements must have both
shortest possible wire connections;
- Chain of communication with the computer should be
away from the chains of video.
As an example, Figure 6 shows
option placement of elements on
board. Communication cable motherboard with ZX-Spectrum
shall not exceed 30 cm
VT2 VT1
R31
D24
VT3
R32
D14
D15 D17
D18
D16 D19
D1 D2 D3
D12 D11 D9
D6 D4 D8 D13
D7 D5 D10 Q1
D23 D22 D21 D20
Interface ZX-Spectrum Catering
Figure 6.
Device Settings VideoPort.
If used serviceable items, the device requires only a
frequency setting line scan resistor R17. When
This device is fully connected to
computer and running the program. If the frequency does not
meet the necessary, the image will be broken the rows.
Adjusting R17 to be achieved normal image on the monitor. If
it does not work, you should look for the cause.
Describe any possible faults or
errors in the installation, as well as the consequences -
quite difficult. Therefore, the author leads
only one recommendation. When looking for faults in the device
should be checked his work in the modes of reading and writing.
For check in read mode to check the timeline formation
addresses signals are read and RAM sampling chip.
Reading mode is carried out under computer control. This
program provides the reading of one screen and goes into
Standby key press. If you press the arrow keys, then the
program will carry out re-reading of the RAM device.
To check the recording mode you can turn off the computer,
and instead of the signal on pin 2 IC D17.1, should give a
signal of zero level. At the same time will go to the recording
mode to RAM. Such a regime work allows you to check timeline of
the device in write mode of RAM. Verification of the interface
device from the ZX-Spectrum must be done in the manner
customary for external devices.
SOFTWARE
Devices VideoPort.
The program consists of a main program
in Basic and loaded the machine unit
codes. Text of the program shown in Listing 1.
Listing 1.
5 29,999 CLEAR: CLS: LET TT = 0: LET NN = 0
10 CLS: BORDER 7: INK 0: PAPER 7
20 RANDOMIZE USR 15619: REM:
LOAD "CODVID1" CODE
41 CLS: BORDER 7: INK 0: PAPER 7:
PRINT AT 10,2; "1-INPUT SCREEN"
1942 PRINT AT 11,2; "two-READ SCREEN OF
DISK "
1943 PRINT AT 12,2; "3-CATALOG"
1944 PRINT AT 13,2; "4-EXIT TR-DOS"
45 LET K $ = INKEY $
1946 IF K $ = "1" THEN GO TO 159
1947 IF K $ = "3" THEN GO TO 60
1948 IF K $ = "4" THEN GO TO 65
1949 IF K $ = "2" THEN GO TO 5000
50 GO TO 45
60 RANDOMIZE USR 15619: REM: CAT
61 LET K $ = INKEY $
1962 IF K $ = "" THEN GO TO 61
63 GO TO 41
65 CLEAR 65000: RANDOMIZE USR 15619:
REM: RUN "boot"
159 IF TT = 0 THEN INPUT "INPUT NUMBER
FILE - "; TT: BORDER 7: PAPER 7: INK 0
160 CLS: POKE 23659,0: PRINT AT 14,2;
"FOR NEW SCREEN - ENTER"
170 PRINT AT 11,2; "SCANING - CURSOR"
180 PRINT AT 12,2; "EXIT IN MENU - e"
190 PRINT AT 17,2; "FOR START - ENTER"
195 PRINT AT 13,2; "FOR SAVE SCREEN - s"
200 IF INKEY $ = "" THEN GO TO 200
220 BORDER 0: RANDOMIZE USR 32768
280 GO SUB 2000
290 IF A = 101 THEN GO TO 4000
310 GO TO 220
2000 LET A = PEEK 32772
2010 IF A = 115 THEN GO TO 3000
2030 RETURN
3000 LET TT = TT
3006 LET F $ = STR $ (TT)
3007 RANDOMIZE USR 15619: REM: SAVE F $
CODE 16384,6912
3010 LET TT = TT +1: RETURN
4000 POKE 23659,2
4010 GO TO 1941
5000 IF NN = 0 THEN INPUT "INPUT NUMBER
FILE - "; NN: GO TO 5130
5010 BORDER 0: LET N $ = STR $ (NN): LET P =
USR 15619: REM: LOAD N $ CODE
5020 IF P = 0 THEN PRINT AT 1,1; NN:
GO TO 5030
5025 CLS: PRINT AT 10,10; "FILE"; NN
5030 LET K $ = INKEY $
5035 IF K $ = "n" THEN LET NN = 0: GO TO 5000
5040 IF K $ = "e" THEN GO TO 4000
5050 IF K $ = "z" THEN GO TO 5100
5060 IF K $ = "" THEN GO TO 5030
5070 IF K $ = "p" THEN LET NN = NN +1:
GO TO 5010
5080 IF K $ = "o" THEN LET NN = NN-1:
GO TO 5010
5090 GO TO 5030
5100 RANDOMIZE USR 15619: REM: ERASE N $
CODE
5120 LET NN = NN +1: GO TO 5010
5130 CLS: PRINT AT 10,2; "NEXT FILE - P"
5140 PRINT AT 11,2; "PRED. FILE - O"
5150 PRINT AT 12,2; "DELETE FILE - Z"
5160 PRINT AT 13,2; "NEW NUMBER FILE - N"
5170 PRINT AT 14,2; EXIT IN MENU - E "
5175 IF INKEY $ = "" THEN GO TO 5175
5180 GO TO 5010
Consider the program. After loading the machine code, the
program will provide the menu:
1 - ENTER PICTURES
2 - READING PICTURES WITH DISC
3 - Browse Catalogue CD
4 - EXIT TO bootstrap TR-DOS
When selecting the input image program requests a file
number and prints on-screen reminder of the key management
when taking pictures:
SCANNING FOR COPIES OF FRAME -
Cursor keys
Save the image - "S"
EXIT to MAIN MENU - "E"
Change picture - "ENTER"
After pressing "ENTER" is launched
machine code from the address 32768. The display
picture appears. If pressed
key "S" or "E", there will be a transition
the main program. Then, depending
of the pressed key, and "S" - will
sohranenie file with the current number, if
"E" - will transition to the main menu,
Line 41. Code keystroke program
receives from the program in machine code through the cell
32772. This cell PRIZN in the text in assembler.
When you select a picture from a disk read takes you to a
line 5000 program. The program asks for the number
file to read from disk and displays memo
the management of this regime.
VIEWING THE NEXT FILE - "P"
View previous FILE - "O"
DESTROY THE CURRENT FILE - "Z"
Enter a new file number - "N"
Go to the main menu - "E"
Next, the program reads the appropriate
file and displays it on screen. If the file
desired number is not on disk, a message about it. Analysis of
the presence of a file is on line 5020. Next, the program goes
on to analyze the key pressed. Sequel to "transparent" and
requires no comment.
Text mashinokodovogo unit recruited at
assembly and is shown in Listing 2.
Listing 2.
ORG 32768
JP BEGIN
UPR DEFB 0; control byte
PRIZN DEFB 0; bytes signs
STR0 DEFB 0; early. Line Screen
; In the frame
BAIT0 DEFB 0; early. B screen
; Line
BUF1 EQU 41550; beginning of the buffer
PDAT EQU 0; port address data
PUPR EQU 3; port management and
PSOST EQU 1; port status
ADR DEFW # 0000 current address
BEGIN PUSH HL; beginning of the program
PUSH BC
PUSH DE
LD A, # 30; setting register
LD (UPR), A; management exodus
OUT (PUPR), A; spectral position
B00 IN A, (PSOST); waiting for the transition
BIT 0, A; device in the original
JR Z, B00; spectral position
B1 DI
LD HL, BUF1; installation address
LD (ADR), HL; Boobs Pictures
CALL INIC; frame in "VideoPort"
B0 CALL SCAN; of RAM devices
; To clipboard ZX
CALL SREN; transformation Buffet
; RA SCREEN
EI
CALL KEY; poll keypad
CP # 09; shift in pictures
JR Z, B3; depending on the
CP # 08; zhatoy keys
JR Z, B4
CP # 0A
JR Z, B6
CP "s"; return to BASIC
JR Z, B9
CP "e"
JR NZ, B1
B9 LD (PRIZN), A
POP DE
POP BC
POP HL
RET
B3 LD A, (BAIT0); computation and mouth
ADD A, 1; permutation of the initial
CP 32; bytes
JP Z, B0
LD (BAIT0), A
JP B0
B4 LD A, (BAIT0)
SUB 1
CP 255
JP Z, B0
LD (BAIT0), A
JP B0
B5 LD A, (STR0); computation and mouth
SUB 8; permutation of numbers on
CP 248; initial line
JP Z, B0
LD (STR0), A
JP B0
B6 LD A, (STR0)
ADD A, 8
CP 100
JP NC, B0
LD (STR0), A
JP B0
INIC PUSH HL; start recording in the RAM
PUSH BC; device
PUSH DE
PUSH AF
IC1 IN A, (PSOST); check bits of
BIT 0, A; preparedness
JR Z, IC1
LD A, # 18, set the
LD (UPR), A; record
OUT (PUPR), A
CALL SBA; reset address
IC2 IN A, (PSOST); check bits of
BIT 0, A; preparedness
JR NZ, IC2
LD A, (UPR); withdrawal signs re
OR # 20; bench press record
LD (UPR), A
OUT (PUPR), A
POP AF
POP BC
POP DE
POP HL
RET
SCAN PUSH HL; start reading mode
PUSH BC; of RAM VideoPort
PUSH DE
PUSH AF
SC5 IN A, (PSOST); waiting for the end
BIT 0, A; pisi in RAM VIDEO
JR Z, SC5; PORT
CALL SBA; reset address
LD A, (STR0)
LD B, A
SC6 LD A, 0; loop installation hell
ADD A, B; rez on the initial
JR Z, SC7; line
CALL SA
DEC B
JR SC6
SC7 LD B, 192; max. number of rows
LD C, 32; max. bytes
LD HL, (ADR); buffer address
SC8 LD A, 0
ADD A, B
JR Z, SC3
LD A, (BAIT0)
LD D, A
SC9 LD A, 0; loop installation
ADD A, D; initial byte
JR Z, SC10
CALL SB; by byte
DEC D
JR SC9
SC10 CALL READ; reading bytes of RAM
INC HL; the following address
DEC C; next byte
CALL SB; by byte
LD A, 0
ADD A, C
JR NZ, SC10; cycle of reading lines
LD C, 32; installation expense. bytes
DEC B; decr. account. lines
CALL SA; by RAM address
JR SC8
SC2 POP AF
POP BC
POP DE
POP HL
RET
SC3 CALL SBA
JR SC2
; Sub output of signals via
; Management
SBA PUSH BC
LD A, (UPR)
OR # 01
OUT (PUPR), A
LD A, (UPR)
OUT (PUPR), A
POP BC
RET
SA PUSH BC
LD A, (UPR)
OR # 02
OUT (PUPR), A
LD A, (UPR)
OUT (PUPR), A
POP BC
RET
SB PUSH BC
LD A, (UPR)
OR # 04
OUT (PUPR), A
LD A, (UPR)
OUT (PUPR), A
POP BC
RET
; Routine reading from data register
READ PUSH BC
LD A, (UPR)
AND # EF
OUT (PUPR), A
NOP
IN A, (PDAT)
LD (HL), A
LD A, (UPR)
OUT (PUPR), A
POP BC
RET
; Routine conversion to the screen buffer
; In the display area of RAM ZX
SREN PUSH HL
PUSH BC
PUSH DE
PUSH AF
LD HL, BUF1
LD B, 0
SR1 LD A, B
CP 192
JR Z, SR2
CP 128
JR NC, SR3
CP 1964
JR NC, SR4
LD DE, # 4000
LD C, B
JR SR5
SR2 POP AF
POP DE
POP BC
POP HL
RET
SR3 LD DE, # 5000
LD A, B
SUB 128
LD C, A
JR SR5
SR4 LD DE, # 4800
LD A, B
SUB 64
LD C, A
SR5 LD A, C
AND # 07
ADD A, D
LD D, A
LD A, C
AND # 38
RLCA
RLCA
ADD A, E
LD E, A
LD C, 32
SR6 LD A, (HL)
LD (DE), A
INC HL
INC DE
DEC C
LD A, 0
ADD A, C
JR NZ, SR6
INC B
JR SR1
; Routine survey of the keyboard
KEY PUSH HL
LD HL, 23611
RES 5, (HL)
K1 BIT 5, (HL)
JR Z, K1
LD A, (23560)
POP HL
RET
B AND D E O P O R T (Part IV)
(C) AlphA Studio
We now turn to the advice and recommendations of the promise
at the outset.
The most extensive recommendation concerns
those users SPECTRUM, which have
in its competence to the parallel port
KR580VV55A. Attaching VideoPort through this
port can throw out a few chips and circuit elements, namely,
D20, D21, D22, D23, D13.6, R6, VD8 and VD9. Signals
going to the chip D20 (IR22), which
Register of data devices connected to
Port A veveshki. READY signal, which was originally
entering the computer through the register D21,
connect to a conclusion C0 (vyv.14) VV55A and
control signals to the device VideoPort -
B port chip parallel port.
For those who want to install on your PC
KR580VV55A chip, I suggest to apply to the article in the ECHO
# 5 (Brest). Below is a diagram connecting the device VideoPort
to your computer via mikruhu KR580VV55A.
A0 April 1917 W
KR580 A1 March 1918 and
VV55A A2 2 19 n
A3 January 1920 and
A4 40 21
A5 39 22 y
A6 38 23 with
A7 37 24 m
p
B0 18 41 on
B1 19 42
B2 20 43 m
B3 21 54 in
B4 22 16 and
B5 23 55
B6 24
B7 25 AND
D
C0 14 39 E
C1 15 O
C2 16 P
C3 17 O
C4 1913 F
C5 12 T
C6 1911
C7 1910
Listing VIDEOPORT'a support programs necessary to make the
following additions and small difference.
Change the port values in the rows:
PDAT EQU # 1F; Port A VV55A
PUPR EQU # 3F; port B VV55A
PSOST EQU # 5F; port C VV55A
Add the program initialization string VV55A:
BEGIN LD A, # 91
OUT (# 7F), A; # 7F - address register
. . . ; Control word
; KR580VV55A
Veveshki port addresses are for computer Baltic, if your
comp they differ, you should substitute your own values.
To simplify the assembly of printed circuit board design, it
may be advisable soldered memory chips one over the other,
tilting the pre-1920 pace. This will save space and simplify
wiring seals.
That's all. You can start assembly. If anything is unclear,
write. Address at the office.
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