Nicron #14 03 января 1997

Железо

Iron - an overview of the microprocessor Zilog Z380, continued.

                          MPU Z380

[Continued. Previous publications in the NN 12,11,10,9,8,7]

(C) WLODEK BLACK

    Group instruction decode directives

Mnemonic Meaning Commentary

DDIR W One subsequent instructions execute in a mode
        "Word"

DDIR IB, W One subsequent instructions execute in a mode
        "Word"; expand immediate operand on the
        1 extra byte

DDIR IW, W One subsequent instructions execute in a mode
        "Word"; expand immediate operand on the
        word (2 bytes)

DDIR IB Extend immediate operand of 1 byte

DDIR LW One subsequent instructions execute in a mode
        "Long term"

DDIR IB, LW One subsequent instructions execute in a mode
        "Long term", to expand direct
        operand by 1 byte

DDIR IW, LW One subsequent instructions execute in a mode
        "Long term", to expand direct
        operand word

DDIR IW Extend immediate operand on the floor.

A characteristic feature of the guidelines is their decoding 
performance in a single machine cycle with the instruction to 
which the directive is decoding, so the actual execution of the 
directive decoding takes 0 (!) More processor cycles.

Previously mentioned, but I will briefly remind you once again 
for what serve as guidelines for decoding. For example, in 
operation     LD E, (IX + d)

displacement "d", which is usually one-byte, you can extend
Up to 2 - DDIR IB LD E, (IX + dd)
or even 3 - DDIR IW LD E, (IX + ddd) - bytes. Well, relative 
addressing a range of + - 8 MB (24-th digit as earlier, signed) 
- enough for any real programs? 

    Command group 16 - and 32-bit arithmetic
            and Logic

New commands:

ADD SP, nn SP <- SP + nn Modifying the stack pointer
SUB SP, nn SP <- SP-nn by the addition or vychtaniya
                with a constant. In the extended
                SP mode, the processor has
                32 significant bits.

ADDW [HL,] pp HL <- HL + pp Addition of HL with another pair pp.
                Differs from ADD HL, pp the influence it at all 
the flags. 

ADDW [HL,] nn HL <- HL + nn Addition of HL with 16-bit by a 
constant (can DDIR) 

ADDW [HL,] XY HL <- HL + XY Addition of HL to IX or IY

ADDW [HL,] (XY + d) HL <- HL + (XY + d) Addition of HL with a 
word (!) From hell rez (XY + d). "D" can be expanded            
     through DDIR 

ADCW [HL,] uu HL <- HL + uu + CY Addition with carry
SUBW [HL,] uu HL <- HL-uu Subtraction
SBCW [HL,] uu HL <- HL-uu-CY Subtract with carry
ANDW [HL,] uu HL <- HL and uu Logical AND
ORW [HL,] uu HL <- HL or uu Logical OR
XORW [HL,] uu HL <- HL xor uu Logical XOR
CPW [HL,] uu HL-uu Comparison with the installation of flags
where "uu" - any operand, as in ADDW; CY - sign transfer

ADD HL, (nn) HL <- HL + (nn) Addition of the word at address 
(nn) SUB HL, (nn) HL <- HL-(nn) Subtract word at address (nn)

                In Advanced mode, the CPU
                (Not "long term"!) - 32 bits.
                In normal mode, the address can be pa sshirit 
through DDIR. 

The "old" team families ADD HL, rr; ADD XY, rr; INC rr; INC XY;
DEC rr; DEC XY in the advanced mode of the processor (meaning
not the regime "long term", and access to 4G memory) work with 
32razryadnymi operands. In normal mode expansion of the 
discharge impossible due to the fact that the SP register in 
the codes of the commands that group is present along with 
other pairs of registers, and he does not expand without having 
to switch the processor into advanced mode. 

[To be continued].