Nicron #11 12 декабря 1996

Железо

Iron - an overview of the microprocessor Zilog Z380, continued.

                          MPU Z380

(Continued from previous publications - Room 10,9,8,7)

(C) WLODEK BLACK.


    Exchange of commands, sending unit and group search.

New commands:

EX BC, DE BC (15-0) <-> DE (15-0) exchange value pairs
EX BC, HL BC (15-0) <-> HL (15-0) major RON.
                    In Long Word mode-32 bit



EX A, r A <-> r exchange 8-bit values
                accumulator and other registers,
                For example, EX A, B; EX A, E.

EX A, (HL) A <-> (HL) exchange values ​​of the battery and
                memory, addressable by a pair
                HL.

EX r, r 'r <-> r' exchange values ​​of 8-bit
                Register and its alternative
                "Double", for example, EX B, B '.

EX pp, pp 'pp (15-0) <-> pp' (15-0) Convert 16-bit values 
​​with values ​​and a pair of alternative                 
couples, for example, EX BC, BC '.                 In Long Word 
mode - 32 bits. 

EX XY, XY 'XY (15-0) <-> XY' (15-0) Convert 16-bit values 
​​with values ​​IX or IY with alternatives nym index register.  
               In Long Word mode - 32 bits. 

EX pp, XY pp (15-0) <-> XY (15-0) Convert 16-bit values ​​with 
values ​​pairs and index Regis spectrum, for example, EX HL, 
IX.                 In Long Word mode - 32 bits.


EX IX, IY IX (15-0) <-> IY (15-0) Convert 16-bit values ​​with 
values ​​between the two index                 registers.

                In Long Word mode - 32 bits.

EXALL SR (1924) <- NOT SR (1924) Switching from the ground to
        SR (1916) <- NOT SR (16) alternative, or vice versa
        SR (8) <- NOT SR (8) sets IY, IX, BC, DE, HL.

EXXX SR (1916) <- NOT SR (1916) Switching from the ground to
        alternate or opposite sets of registers IX

EXXY SR (1924) <- NOT SR (24) The same for IY.

Please note: due to software availability register SR
primary and alternate set of registers are not equal! Software 
can determine which of the set of assets! Because of this 
should be clearly distinguished EXCHANGE values ​​between 
registers and Set switching register!


SWAP pp pp (31-16) <-> pp (15-0) exchange value of the high
        and the youngest a 16-bit 32-bit half of the pair. For 
example, SWAP HL. Operates independently of the         set 
format operand word length. 

SWAP XY XY (31-16) <-> XY (15-0) Same for the IX, IY.

LDIW (DE) <- (HL) Sending a single
        (DE +1) <- (HL +1) words. Address of DE <- DE +2 source 
of HL <- HL +2 receiver must be         BC (15-0) <- BC (15-0) 
-2 even.         LDI from this team is different in that in one

        machine cycle forwards word, and not
        bytes.

LDDW (DE) <- (HL) Shipment words since Dec (DE +1) <- (HL +1) 
rementom addresses.         DE <- DE-2

        HL <- HL-2
        BC (15-0) <- BC (15-0) -2

LDIRW Similar command group forward words.
LDDRW runs until BC reaches zero.

General properties LDIW, LDDW, LDIRW, LDDRW:
- In the "longest word" sent two words in one machine

  cycle, and BC reduces its value by 4;
- The address of the source and receiver region should be 
expressed   vneny to even address (which will otherwise 
described   description of silent);

- Using the "Z80" Addressing looped for Junior 64K.


Group of commands such as CPI, CPIR not expanded and remains 
the same. In It also holds zakoltsovannost address within the 
64K in non-dilated mode of the processor.

"Old" EX DE, HL; EXX; EX (SP), HL; EX (SP), XY in the "long
the word "work with 32-bit registers in pairs.
For EX (SP), rr holds everything that was said about 
zakoltsovannosti addresses. 

         Group 8-bit arithmetic and logic.

Declared "legitimate" operations with the halves of the index 
registers: 

ADD A, XYU
ADD A, XYL
and everything related to them - ADC, SUB, SBC, AND, OR, XOR, 
CP, as well as increment and decrement operations: 

INC XYU DEC XYU
INC XYL DEC XYL

New operations:

TST r A AND r logical AND of the accumulator
                and the second operand with the installation
flags, but no infiltration result in the battery. (R - all 
valid ways of addressing an operand - both for AND). 

TST n A AND n Same with the constant in the role of the second 
operand. 

TST (HL) A AND (HL) Same as on the contents of the cell, hell 
resuemoy pair HL. 

[To be continued].