Beginners - "Iron" logic.

 ──────────────────── ────────────────────
 "Iron" logic.
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 (c) VTS'99

   So, last time we stopped at
triggers. I'll go back a little and belt-
nude circuit design of RS-, D- and T-flip-flops.


 RS trigger.

 _ ┌──┐ ┌──┐
 S ───┤ &│ R ────┼ 1│
 ┌─┤ o─┬── Q ┌─┤ o─┬─── Q
 │ └──┘ │ │ └──┘ │
 └──/──┘ └──/──┘
 ┌──/──┐ ┌──/──┐
 │ ┌──┐ │ │ ┌──┐ │
 _ └─┤ &│ │ _ └─┤ 1│ │ _
 R ───┤ o─┴── Q S ────┤ o─┴─── Q
 └──┘└──┘

The principle of operation is simple: while the controls
signals are inactive (i.e. 0 for direct and 1
for inverse), no one pays attention to them
attention, and you get a ring of two in-
vectors, having two stable states
nia.  The influence of the control signal
throws the first or second shoulder accordingly
correspondingly, and then (along the ring) and counter-
positive.  If the trigger is in non-
in the current state, nothing changes.
   It should also be noted that
simultaneous action of both controls
other signals are prohibited,because
the state of the trigger after this is uncertain
but (the JK trigger does not have this drawback).


 Clocked RS trigger.

 ┌──┐ ┌─┬──┐
 R ───┤ &│ ┌─┬──┐ ─┤S│ T├── Q
 ┌─┤ ├──┤S│ T├─ Q │ │ │
 C ─┤ ├──┤ │ │ │ ─┤C│ │
 └─┤ &│ │ │ │ _ │ │ │ _
 S ───┤ ├──┼R│ o─ Q ─┤R│ o── Q
 └──┘ └─┴──┘ └─┴──┘

   You can write information into this trigger
tion only when signal C is active, in this case
In the normal case - 1. (for inverse input C
just add an inverter). For trigger
ra with inverse inputs can be used
OR gates are used as gates (then
input C is also inverse).


 (clocked) D-trigger.

 ┌─┬──┐
 D ───┬───────┤S│ T├── Q ┌─┬──┐
 │ │ │ │ ─┤D│ T├── Q
 C ───)───────┼C│ │ │ │ │ _
 │ ┌──┐ │ │ │ _ ─┤C│ o── Q
 └─┤1 o──┤R│ o── Q └─┴──┘
 └──┘ └─┴──┘

   This trigger is elementary
memory cell with a capacity of 1 bit. Input
data is supplied to input D and written
by signal C and are stored until the next cycle
la records. In this case, the state of the input D
normalized.


 Counting T-trigger.

 ┌─┬──┐ ┌─┬──┐
 ┌─┤D│ ├───── Q │ │ T├── Q
 │ │ │ │ _ ──/T│ │ _
 T ──)─/C│ o─┬─── Q │ │ o── Q
 │ └─┴──┘ │ └─┴──┘
 └────────┘

   This trigger can be built on OS-
new D-trigger with dynamic control
I eat, i.e. edge triggered (icon /
in the notation) or decay () of the timing
signal.  As can be seen from the diagram, with each
front, the opposite will be recorded in it
position.


 Universal JK trigger.

 ┌─┬──┐
 ──┤S│ T│
 ├─┤ ├── Q
 ──┤J│ │
 ──┤C│ │
 ──┤K│ │ _ ├─┤ O── Q
 ──┤R│ │
 └─┴──┘

 Based on the JK trigger, you can build
any of the above.
 Asynchronous inputs R and S may be absent
to say
   Clock input C allows the passage
signal J and K. Input J is similar in
destination S, input K - R. Howeverwith one
there are no simultaneously active J and K indefinitely
things - the trigger is thrown in the opposite direction
positive state (similar to T-trigger
ru).


 Two-stage trigger.

   This can be any of the clocked
triggers, consider a two-stage
D-trigger.
   Two-stage triggers are also called
master-slave triggers, or master-assistant
nickname.

 ┌─┬──┐ ┌─┬──┐
 D ───┤D│ T├────┤D│ T├── Q
 │ │ │ │ │ │ _
 C ─┬─/C│ │ ┌─/C│ o── Q
 │ └─┴──┘ │ └─┴──┘
 │ ┌──┐ │
 └───┤1 o──┘
 └──┘

   As can be seen from the figure, the first trigger
triggers on the front, and the second - on the decline
timing pulse.  Those.  information
is accepted into the master trigger along the front, and
issued to the output (to the helper trigger) by
decay of impulse C.
   This type of triggers is used, for example,
measures, in multi-digit counters and registers
shift rah.

 to be continued...

   Next time I'll focus on more
complex elements and units.