><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><
░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓
▓░▓░▓░▓░▓░▓░▓░▓███████▒░▓░▓█████▒░▓░▓█████▒░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░
░▓░▓░▓░▓░▓░▓░▓░▓░▓░██▒░▓░▓██▒░░██▒░▓██▒▓░██▒░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓
▓░▓░▓░▓░▓░▓░▓░▓░▓░██▒░▓░▓░▓█████▒░▓░██▒░▓██▒▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░
░▓░▓░▓░▓░▓░▓░▓░▓░██▒░▓░▓░▓██▒░░██▒░▓██▒▓░██▒░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓
▓░▓░▓░▓░▓░▓░▓░▓░██▒░▓░▓░▓░██▒░░██▒▓░██▒░▓██▒▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░
░▓░▓░▓░▓░▓░▓░▓░███████▒▓░▓░█████▒▓░▓░█████▒▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓
▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░▓░
><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><
Здесь мы хотим представить вашему драгоценному вниманию инфор-
мацию ранее не публиковавшуюся нигде ! Перевод оригинального
описания к эмулятору господина G.A. LUNTER'a выполненный на
вполне и вполне профессиональном уровне.><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><
(C) Translation and editing by Alexey Voskresensky'97
The Z80 processor is a completely honest processor and I don’t remember how
some interesting 'bugs' and 'tricks'. However, I refuse
Several undocumented 'gadgets' fell. Some of them
quite useful, some not. For some time now, many programs
ramm use useful ones, and a minority use strange and
incomprehensible. I, in turn, will try to describe them to you.
Most Z80 operation codes (OCs) are one byte long.
well; possible bytes or words of the operands do not count. Four OK -
#CB, #DD, #ED and #FD are interchangeable shift codes: they change
the meanings of the codes following them.
There are 248 different #CB opcodes. Code block #CB30 to
#CB37 'dropped' from official descriptions. These instructions are usually
were indicated as mnemonics SLL, Shift Left Logical (logical
shift left - approx. ), command action: shifts the op-
rand and sets bit 0 to one. "Bounder" and "Enduro Racer"
use them.
OK #DD and #FD precede instructions using registers
IX andIY. If you look carefully at these instructions, it is easy
understand how they work:
#2Ann LD HL,(nn) #DD2A nn LD IX,(nn)
#7E LD A,(HL) #DD7E d LD A,(IX+d)
OK #DD just changes the value in the next statement. If byte
memory is addressed indirectly through HL, as in the second example
an offset byte is added. Otherwise, the instructions simply affect the re-
hystr IX instead of HL (clumsy notation system, extra cl-
sweat to assembler and disassembler writers: JP (HL) is not
indirect addressing; this essentially means JP HL).
If OK #DD precedes an instruction that does not use register
first pair HL, then the instruction is executed as usual (this is a good
a technique for hammering the brains, let's take note - approx.). Them
at least, if the instruction operates with the H or L register, then
the high or low half of the register will be used
pairs IX:
#44 LD B,H #DD44 LD B,IXh
These types of informal instructions are used by many
programmers. By the way, a lot of alternating #DD codes and
#FD will be equal in efficiency to NOPs. They don't do anything
will, with the exception of re-setting the 'flag, refer to HL
as to IX (or IY)' and will take exactly 4 measures each (pop-
Please let MONS disassemble such a block). *
* - I'm sure he'll throw up - approx.
I haven't metprograms using unofficial #ED -
instructions, with the exception of #ED6B nn, long option #2A nn,
LD HL,(nn). I don't know the others. However, I'm quite sure that
they exist, but I will never take on the terrible task of checking
eat them all.
About the R register. In general, this is not completely undocumented
'carnation', although I don't remember any really complete
th description of this thing. Register R is a counter that is
updates' each instruction, #DD,#FD,#ED and #CB will be considered
appear as separate instructions. Shifted instructions will increase
R for two. Note the curious exception: twice
shifted OK (#DDCB and #FDCB) will also increase R by two. LDI Team
will increase R by 2, LDIR by BC*2, the LDDR command will do the same
and others like her. The sequence LD R,A LD A,R will increase A by
two. The exception is the most significant bit: in the R register this bit is low
when it doesn't change. This is explained by the fact that several years ago
back everyone used 16K chips. Inside such a chip, the bits are grouped
copied into a 128x128 matrix needing 7 bit refreshing
cycle. Therefore, ZILOG decided to use only the lower 7
bit.
You can easily check how critical the register R 'is
lays down the memory. Assemble the following program:
ORG 32768
D.I.
LD B,0
LOOP XOR A
LD R,A
DEC HL
LD A,HOR L
JR NZ,LOOP
DJNZ LOOP
EI
RET
The program will run for about three minutes. Look at the top ones
32K RAM, for example UDG graphics. It's destroyed. Only a few
the first bytes in every 256 byte block still contain zeros
because they were 'updated' during the LOOP
ULA is keeping an eye on the bottom 16K RAM upgrades.
-=- TO BE CONTINUED -=-
______________________________________________________________
Share your thoughts about the article