Direct access sound card
(DMA Sound Card)
A little history.
A long time ago, when pioneers (and com-
Somoltsy), when the ultimate dream of a musician was electrohy-
container and when computers were just making their first squeaks,
already then there were people who thought - “why not
Can you make the computer play some tune?" And
forced... Since then, computer (under "computer mu-
"language" often means all synthesizer music, but
This means music performed only on a computer.
re WITHOUT external synthesizers, MIDI, etc.) became unchanged
an attribute of games and demonstrations. As one of the greats said:
"good music can raise a trivial program to
level of extraordinary, and excellent to the level of sensational." C
With the development of computers, sound production methods were also improved.
treatment. And here there are two main methods.
The first method - FM synthesis, originates from the first
"speaker" music. It is based on the addition of several co-
vibrations of various forms and frequencies. Here, the more fold-
frequencies (elementary oscillators), the closer the sound is to the
father-in-law. Professional synthesizers use 32
and more oscillator per voice. Naturally, such a thing costs
a lot of money and therefore in sound cardsusually used
from 1 to 4 oscillators. For example, AY8910/12 uses 3 oscillators
rectangular lator + sawtooth envelope, or
triangular shape. In addition, many sound cards have
There is a certain set of “tools”, i.e. frequency tables
for adding the recorded
in the ROM of the card and with which, often, the sound of this card and the
limited. These are, for example, Adlib/Sound Blaster for PC or
SEGA Genesis/Megadrive. The advantages of this synthesis method
are small amounts of memory for music and data flow, one
However, the set of sounds is very limited. Therefore, increasingly this
the method is being replaced by another - the sampling method.
The second method is based on playing a pre-digitized
nal sounds (samples). Much more memory is required here
but ANY sounds are available. The main parameters are here -
bit depth of digital-to-analog converters (DACs), number
in channels, sampling frequency. The de facto standard for
such cards are AMIGA. It has 4 eight-bit ca-
nal with a sampling frequency of 3.54 MHz. In addition, thunder
the bone on each channel can be software adjusted from 0
up to 64 conventional units SoundBlaster/PC and SEGA have 1 eight-bit
channel with a sampling frequency of up to 44 kHz and therefore uses
are used mainly for reproducing digitized effects in
games. GUS/PC has the best parameters. It has 2 sixteen-
Tibit channels with a sampling frequency of 44 kHz andown
new processor and memory on the board. All of the above statements
swarms are active, i.e. not requiring a processor
time. In addition, there are a lot of passive devices
Covox type, i.e. DAC on some port. Here to talk about
some parameters does not make sense, since the sound is like this
"cards" strongly depends on the processor performance, on
type of mixing, sample stability, software environment
marriage, etc. etc.
What about the ZX SPECTRUM? So far we are seeing sluggish pro-
process of connecting Covox, which are unlikely to satisfy even
computer sound fans. The truth is being developed in St. Petersburg
General Sound sound card, but so far we can only hear promises and
odes of praise. I in no way want to offend the developers.
kov of this card, but the parameters are 4 eight-bit channels with a clock
That sampling rate of 37.5 kHz can hardly topple the Amiga-
nikki in a trance, and pisishnikov in shock. I don't argue, there may be sound
not bad, but, as we see, it’s far from the Amiga. In addition 11OkB
to the music... it won't be enough! The advantages of this card include
complete independence from Spectrum, but increase many times over
firmware requirements that are completely inaccessible
neither for study nor for modification by the programmer. This way
So, we see a typically pisish approach to sound - “here’s to you
"black box", there are games for it, what else do you need? Od-
However, so far there has rarely been any borrowing from the PCsuccess
on the Spectrum (remember IS-DOS or CGA-like video modes).
Therefore, one of the main tasks of this development is
was the closest approximation to AMIGA equipment, both
digital audio standard. Let's describe in more detail how the Amiga
plays sound. Data for each channel is transmitted
direct access from memory. The sampling resolution is
0.28 µs (corresponding to a frequency of 3.54 MHz). Array of re-
The given data can have a length from 2 bytes to 128 kb, except
Moreover, array transfer can be looped from arbitrary
places. All channels are completely independent. To play music
languages, an interruption frequency of 13 to 102 Hz is used, during
time at which notes are selected, channels are reprogrammed and
etc.
As you can see, for normal music playback you need
dim direct memory access (DMA) controller and controller
interrupts. Unfortunately, neither one nor the other is available on the Spectrum.
Therefore, the author proposes the following device. The main thing is
purpose - reproduction of Ch-channel, 8-bit music
ki. Those who are interested in other possibilities - see the section
"Prospects".
Description
The device consists of 3 functional blocks: control
DMA roller, interrupt controller, DAC unit. The device has
There are 4 independent, 8-bit audio channels of direct access
to memory. Each channel has6-bit volume control
bones. Sampling resolution per channel is 0.28 µs (3.5 MHz).
It's a little different from the Amiga (3.54 MHz), but also on the Amiga
this value is not constant, but depends on the type of video processor
(PAL or NTSC), secondly the difference is about 1%. Straight
my access is to all memory, which is ectx in
Spectrum (128,256,512,1024 kb) and does not depend on the config port
guration, the maximum length of the transmitted array is 64K. Cont.
The interrupt roller handles four types of interrupts:
end of direct access cycle, two independent timers
interrupts and standard frame interrupts. Each type of pre-
interrupts are identified by a bit in the interrupt vector, each
type of interruption, including personnel interruption, can be masked
is in the mask register. By reset, direct access and all interruptions
positions other than personnel are prohibited.
The port decoder is made on DD1,DD2. Signals
CSD,CST1,CST2,CSP and CSI select DMA controller, 1st timer,
2nd timer, DMA bank register and interrupt mask register.
Signals CSV1-CSVЧ select channel volume registers.
The direct access controller DDb generates the necessary
request signals of the bus issuing 16 bits of address and sampling
external device. DDЗ disconnects the RD and WR signals from the con-
DMA roller and, together with DDЧ.1, generates the MREQ signal in
direct access cycle. Permission to issue a direct mail address
blunt indicates the signal AEN(AdressENabled).
DD7 switches address lines in order to transfer
these addresses of the DMA controller ports and provide addressing
res port with a fixed lower half of the address.
The bank register is made on DD8.1, DD8.4 and DD9. Let's explain
terminology: usually memory bank and memory page are considered
are considered equivalent concepts. However, we will consider
Let's think about these concepts a little differently. The page implies-
This is a regular ZX128 memory page, but we will call it a bank.
create four consecutive memory pages starting from the one
measures of which is a multiple of 4m. So the 0th bank consists of #10, #11, #12 and
#13 pages, 3rd of #54,#55,#56 and #57, etc. (pages given
for Pentagon S12, for machines with two control ports pa-
page numbers will be set differently, but the general
the principle remains the same). For each DMA channel a memory bank
is set independently.
Programmable timers DD10, DD11 generate the necessary
reference frequencies for requesting DMA channels (channels 1 and 2) and
interrupts (channels 3). All channels operate in 2nd mode (de-
frequency dilator).
DD12 generates signals for writing a data byte to a register
DAC in direct access loop. The software registers of the DAC are insufficient
stupid.
Buffer register DD13 stores the high half of the address
DMA at the beginning of the loop and then outputs it to the address bus. Image
Please note that signals A14',A15' are not sent to
Z80, and RAM for multiplexers.DD14 generates a DMA request signal of the required duration
ness. Because The DRQ signal must be kept active until
confirmation appears with the DACK signal, and DD10,DD11 form
pulse duration 0.28 μs.
Due to the fact that K181OVTZ7 autoloads (unlike
AMIGA) is only possible from the base address, i.e. impossible
loop sample from an arbitrary address, so for looping
When transferring sample, a vector interrupt at the end of the transfer is used.
DMA dachas.
The interrupt controller is assembled on DDS.6, DD8.2-3,
DDCh.1-3, DD15-DD19. DD18 is the interrupt mask register. He
allows you to programmatically allow or disable certain types
interrupts. DD16 - interrupt vector register. Interruptive
the device resets the corresponding bit, then in a loop
interrupt confirmation DD17 outputs a vector to the data bus
interrupt whose four most significant bits are set or
reset depending on which devices are set
interrupt request. This solution made it possible to do without
hardware priority control. All interrupts are equal
priority and with the simultaneous arrival of two or more pre-
jerks, the interrupt vector changes. (see Programming)
After the interrupt is acknowledged, the vector register is cleared
(set to 1).
The DD15.2 request trigger is used to store the pre-
tearing. If at the moment of arrival of an interruption from any use
specific interrupt handling inprocessor is disabled (by command
DI), then the request trigger is reset to 0 and stays like that until
the processor will not be allowed to handle interrupts (by the EI instruction) and
only in the interrupt confirmation cycle will it be set again to
1. This is necessary in order not to miss interrupts,
which arrive at a time when their processing is prohibited
(DI). Moreover, if during the ban period two DIFFERENT
interrupts (not necessarily simultaneously), then programmatically it
it will look as if two types of interrupts arrived at the same time
definitely immediately after the EI command. All this does not apply to cad-
new (standard) interrupt, which has the same length
activity, phase, etc., as before. If any type
interrupts are masked in the mask register, then it is completely
ignored.
Connection
Unfortunately, no computer has the ability
connect any devices with access to more than bCHKB memory,
nor INT intercepting devices. Therefore, unfortunately, without a soldering iron
cannot be done... It is necessary to provide the computer with the possibility
the possibility of transferring senior address lines A14', A15', A16',
A17', A18'. These are not processor address lines, not
output of configuration registers, and address lines that are not
mediocre go to RAM multiplexers. The Pentagon needs
do the following: 15D14 cut off from the ground and apply to it
AEN from device, A14'supplied to 4D14, A15' to 7D14, A16'
on 9D14. On an expansion board up to 512K you need to do the following
changes: connect 7 and 9, 6 and 10, 5 and 11, 4 and 12, 3 and 13
legs KP12, 15 cut off from the ground and place on it AEN, 1
you need to apply AEN, cut 1 LE1 from 5D18 and apply to A17i, to
5D18 submit A17'. INT must be cut off from 16Z80 and fed to INT
devices, send INT' from the device to the 16Z80.
The remaining signals are sent to the corresponding Z80 legs.
Programming
All device ports have low byte address #77.
The high bytes of the address are:
DMA controller -
#0C,#1C,#2C,#3C,#4C,#5C,#6C,#7C,#8C,#9C,#AC,#BC,#CC,#DC,#EC,
#FC
First timer - #3D,#7D,#BD,#FD
Second timer - #3E,#7E,#BE,#FE
Channel banks - #07,#17,#27,#37
Channel volume - #3F,#7F,#BF,#FF
Interrupt mask - #F7
For a detailed description of the DMA controller, see Appendix I.
To work with sound, the controller must be programmed
in single transmission mode, channel priority can be
both simple and cyclic.
Timers set the sampling rates of DMA channels and interrupts.
ny. Channels 1 and 2 of timers are clocked at a frequency of 3.S MHz, and
channels 3 - frequency 1.7S MHz. Channels 1 and 2 of the first timer
set the frequency on DMA channels 1 and 2, channels 1 and 2 of the second
The timer is set to the frequency on DMA channels 3 and 4. All Thai channels
measures should work in the secondmode (programming
timers, see Appendix II).
Bank registers establish the memory bank with which
there will be an exchange. Bank registers contain senior
page number bits, the least significant two bits are included in the direct address
th access. For example, you need to pass an array that is
found on page #16 from address #d8e7. The least significant two bits are
page measure %10, for a DMA address these will be the two most significant bi-
ta. Thus we get DMA bank #01 address #98e7. Fig.1
illustrates converting page number to address and number
bank for Pentagon S12 and Profi1024
PentagonS12
#7ffd Address
┌─┬─┬─┬─┬─┬─┬─┬─┐ ┌─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
bits│7│6│5│4│3│2│1│0│ bits│f│e│d│c│b│a│9│8│7│6│5│4│3│2│1│0│
└┬┴┬┴─┴─┴─┴┬┴┬┴┬┘ └─┴─┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┘
│ └─────┐ │ │ └─────────┐ │ │ │ │ │ │ │ │ │ │ │ │ │ │
└─────┐ │ │ └─────────┐ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
┌─┬┴┬┴┬┴┐ ┌┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┐
bits │3│2│1│0│ bits│f│e│d│c│b│a│9│8│7│6│5│4│3│2│1│0│
└─┴─┴─┴─┘ └─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┘
Bank Address
Profi1024
#dffd #7ffd Address
┌─┬─┬─┐ ┌─┬─┬─┬─┬─┬─┬─┬─┐ ┌─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
│2│1│0│ │7│6│5│4│3│2│1│0│ │f│e│d│c│b│a│9│8│7│6│5│4│3│2│1│0│
└┬┴┬┴┬┘ └─┴─┴─┴─┴─┴┬┴┬┴┬┘└─┴─┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┘
│ │ └───────────┐ │ │ └──────┐ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ └───────────┐ │ │ └──────┐ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
└───────────┐ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
┌┴┬┴┬┴┬┴┐ ┌┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┬┴┐
bits │3│2│1│0│ │f│e│d│c│b│a│9│8│7│6│5│4│3│2│1│0│
└─┴─┴─┴─┘ └─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┘
Bank Address
Fig.1 Converting page address to DMA address
The array cannot cross the boundary of 4 pages, i.e.
can be in #10,#11,#12,#13 pages, but cannot
be in pages #13 and #14, such arrays must
transmit in two times using end-of-transmission interrupt,
or align along the border of 4 pages.
Channel volume registers set the volume to
ranging from 0 (no sound at all) to 63 (maximum
volume). The volume registers are 6 bits wide, so
then the value of 64 is 0, unlike the Amiga, where 64 is the maximum
low volume.
The interrupt controller issues a century in the confirmation cycle.
interrupt torus, which indicates which devices have sent
interrupt request. The interrupt vector has the following
structure:
bit 7 - set to 1 if a frame interrupt has arrived
value, otherwise reset;
bit 6 - reset to 0 if an interrupt arrives from the 2ndtimer, otherwise set;
bit 5 - reset to 0 if an interrupt arrives from 1
timer, otherwise set;
bit 4 - reset to 0 if the end interrupt has arrived
transmission on any DMA channel, otherwise
is installed. In order to determine which channel is
completed the transfer, it is necessary to read the control status register
DMA roller;
bits 3 - 0 are always set to 1.
If several interrupts arrive at the same time, then
several bits are set accordingly
depending. For example
#FF - frame interrupt;
#3F - interrupt from the 2nd timer;
#5F - interruption from the 1st timer;
#6F - interrupt the end of transmission;
#BF - frame interrupt and 2nd timer;
#EF - frame interrupt and end-of-transmission interrupt; and
etc. Vector #7F does not correspond to any device, but how
practice has shown on average once every five minutes such a vector
“slips” and also needs to be processed. Corresponds to him
corresponds to a frame interrupt that occurs at the moment you call
completing the EI team.
The mask register allows you to mask individual types of pre-
tearing. The bit layout is like this:
7 6 5 4 3 2 1 0
┌─┬─┬─┬─┬─┬─┬─┬─┐
│x│x│x│x│0│1│1│1│
└─┴─┴─┴─┴┬┴┬┴┬┴┬┘
│ │ │ └─── allows interruption of the end of the transmission;
│ │ └───── enables interruption of the 1st timer;│ └─────── enables interruption of the 2nd timer;
└───────── allows frame interruption;
Unlike other interruptions, personnel interrupts are not allowed
1 and 0.
Problems
1) The main problem is K58OVI5Z, which consistently does not work
They work in turbo mode with a short IORQom and have a maximum
low frequency CLK 2 MHz. The best solution is to use
shortage of imported 8253, but this is a terrible shortage both in Donetsk and in
Kharkov. As for VI5Z, as practice shows,
They creak, but withstand a clock speed of 3.SMHz. But not you-
wear short IORQ on turbo Pentagon.
2) In some computers it is necessary to provide blocks -
routing port #77. (In Scorpio, the port responds to this address
attributes, which are best cut out completely).
3) It is theoretically possible for the card to work with the 128th Spectrum
mom, however, practically, for the full disclosure of all possible
In reality, you need a machine with a memory capacity of at least 512K. First of all
output, the average volume of music modules is 120 - 250 KB and only
units have a volume of more than 400K, i.e. you will be able to listen
create and use 99% ready-made modules; secondly, if
embed music into any ready-made programs, then all
The 128th memory is jam-packed with these same programs, but
only a few use memory over 128K (RAM disks and other
resident nonsense does not count); and thirdly, if we assume
live thatThe Spectrum platform will develop, then the transition
on a model with memory >128K is inevitable, and if we assume that
ZX128+BETA DISC+AY limit, that's what we're talking about here.
4) To mix channels, the simplest re-
resistive mixer, but perhaps some active or cor-
a rectifying mixer would be better.
5) A voltage of -12V is required (it is possible to use
converter such as in ATM)
Prospects
The author understands that the manufacture and connection of this
maps is associated with quite great difficulties, but this
a consequence of problems that have not been resolved since the past decade-
Tia. Despite the "bells and whistles" in the latest models (Scorpio,
Profi, Atm), these questions still remain open.
Therefore, this development not only provides excellent sound, but
and indicates ways to solve problems that were previously solved
using the “oh, Z80, let’s go!” method. or they didn’t dare at all.
1) It is possible to connect up to four input/output devices
water. These can be ADCs, digitizers, multicards, video
processors and much more. The main advantage is the processor
completely unloaded from both I/O operations and waiting
results. So a “hard drive” connected through a piss room
the multicard will send data directly and can
programmable by its own interrupt.
2) Possible cascadingconnecting another controller
ra DMA (+3 chips)
3) Memory-to-memory transfer is possible.
The "DMA Sound Card" diagram is in the application, in text form.
-=-
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