SIMM & Speccy
(C)JtN/4D/10.03.99
I may disappoint you, but there will be no schemes. And not at all because...
Well, I'm lazy, as usual. Basically, if you are the owner
regular Pentagon, Scorpio, or “uncolored” (in CP/M co-
Surely) Pros, then there are no problems. Of all the others, I only know
Pro (versions 4 and 5). They require 2 bytes to be read simultaneously
that one is from RAM, but this is not so difficult (write to whoever needs it).
Now some background information: DRAM chips are organized
called in the form of a matrix, the rows and columns of which are selected by him-
RAS (Row Access Strobe) and CAS (Column Access Strobe) pulses.
To save information for each row of the matrix, it is necessary to
grow with a period of about 3OOmc. In pC, the signal from the counter is expressed
loaded every 1Smkc, causes an idle cycle of access to the pa-
memory to regenerate the next line. DRAM chips have em-
bone up to FMbit, access time 50-25Ohc and organized by 1 or 4
bit in the case. The digital part of the microcircuit designation looks like:
NC-T, where N=1.4 - cell width, bits; C=64,128,256,000... -
number of cells
(64:64K, 000:1M);
T - access time in nanoseconds or tens of nanoseconds.
Microcircuits can be packaged in DIPkopnyca, installed in
cribs; assembled into SIPP (Single InLine Pin) modulesPackage) and
SIMM (Single InLine Memory Module), installed in a special
new nests. SIPP modules have 30 pins, SIMM 30 or
72 printed outputs. SIPP - rarely used, coincide in size
vodka with standard SIMM ZOpin.
Connection. If you have a regular Spectrum without any color
(advanced) modes, that is, you do not need to
moment of time to read more than one byte from memory, then connect
comes down to installing one register or buffer (as convenient
her) and regeneration of 10 and possibly 11 bits - additional lines
modules (SIMMs have 2 (and some 4) times more lines,
than RU7 and therefore they need to be regenerated). But basically,
if signals MA8, MA9 are thrown to ground, then you can do without
regeneration, while losing a significant part of the memory. Couple
advice: because in all Spectrums the memory is regenerated by video
controller (VC), then regeneration signals should be looked for there.
Find the VC signals that are fed through multiplexers to
MAO-MA7 at a time when /RAS=0 - i.e. active These signals in re-
generations are not involved, therefore they can be used,
choosing from them the one whose frequency is higher (in Pro it’s DA11, in
Scorpio (possibly!) ARF) - let's call it DAr. Next we cut it off
and connect the multiplexer input to ground, also find the signal
address bus of the processor (let's call it Ar), corresponding to DAr and
cut frommultiplexer - this bit (multiplexer input) increases
reduces memory by 2 times, i.e. it needs to be hung on some
port The remaining signals: Ar and DAr need to be assigned to their own
multiplexer (see Fig. 1), from which we will have one more bit
memory expansion. Thus, having regenerated one bit
By blowing you will quadruple its capacity! And finally, one more problem.
It lies in the fact that SIMMs do not have separate inputs and
data outputs, and in most Spectrums they are separate, i.e.
to read from memory, an internal bus is used, with which
data is sent through registers to the video or processor bus
(CPUmemREG). But it’s not all that bad here, we just set the register
on the contrary, relative to CPUmemREG, which will open in
memory recording time (see Fig. 2). If someone has a som-
opinions on performance - I’ll say that I’m doing pretty well
has been working for several months now. Note: During connection
Simm ZOpin it turned out that its CAS signal is inverse, that is,
If you connect Simm 72pin, then you hang CAS on CAS, and if ZOpin,
then don't forget to invert it first. Now turn it on
Simm and work with the DOSa by Reanimator version (4.12F).
Appendix.
Fig.1
┌──┬────┬─┐
GND──6┤A0│ │ │7
DAr──5┤A1│ │A├──MA8
EXb──4┤A2│ │ │
Ar──3┤A3│KP12│ │ MA9--> SIMM
GND──1┤0E│ │ │ CPU - active when
├──┤ │ │ CPU have access to
14│SE│ │ │ memory
/RAS───┤0 │ │ │ EXb -> Extended port
CPU──2┤1 │ │ │ DAr, Ar - see above
└──┴────┴─┘
Рис.2
2┌────┬────┬────┐14 ┌──┬──┬──┐
DB──┤ DC │ │ D ├──DB'┌ ┤ 0│RG│0 ├ ┐
├────┤DRAM├────┤ │ ┤ 1│ │1 ├ │
┌ ┤ A0 │ │ │ │ ┤ 2│ │2 ├ │
│ ┤ A1 │ │ │ DB│ ┤ 3│ И│3 ├ │DB'
│ ┤ A2 │ │ │ │ ┤ 4│ Р│4 ├ │
MA│ ┤ A3 │ 565│ │ │ ┤ 5│ 2│5 ├ │
│ ┤ A4 │ РУ7│ │ │ ┤ 6│ 2│6 ├ │
│ ┤ A5 │ │ │ └ ┤ 7│ │7 ├ ┘
│ ┤ A6 │ │ │ 9├──┤ ├──┤
│ ┤ A7 │ │ │ +5В──┤ C│ │ │
└ ┤ A8 │ │ │ 1│ │ │ │
├────┤ │ │ WE──┤0E│ │ │
RAS─┤/RAS│ │ │ └──┴──┴──┘
├────┤ │ │
CAS─┤/CAS│ │ │
├────┤ │ │
WE─┤/WE │ │ │
└────┴────┴────┘
DB - CPU DATA BUS.
DB'- SUB DATA BUS - внутр. шина памяти.
Таблица 1.
Организация модулей SIMM.
┌───────┬────────────────┬───────────────┐
│Емкость│ С паритетом │Без паритета │
│ ├────────┬───────┼──────┬────────┤
│ BYTE │ ЗOpin │ 72pin │ЗOpin │ 72pin │
├───────┼────────┼───────┼──────┼────────┤
│ 256K │ 256K*9 │ - │256K*8│ - │
│ 1M │1M*9 │256K*36│ 1M*8 │ 256K*32│
│ 2M │ - │512K*36│ - │ 512K*32│
│ 4M │ 4M*9 │ 1M*36 │ 4M*8 │ 1M*32 │
│ 8M │ - │ 2M*36 │ - │ 1M*32 │
│ 16M │ - │ 4M*36 │ - │ 4M*32 │
│ 32M │ - │ 8M*36 │ - │ 8M*32 │
│ 64M │ - │ 16M*36│ - │ 16M*32 │
└───────┴────────┴─── ────┴──────┴────────┘
Table 2.
Pin assignment of SIMM ZOpin modules.
┌────┬─────┬─────┬────┬─────┬─────────┐
│Pin │ STD │ IBM │Pin │ STD │ IBM │
├────┼─────┼─────┤────┼─────┼─────────┤
│ 1 │ +5V │ +5V │ 16 │ DBCh │ DBCH │
│ 2 │ CAS │ CAS │ 17 │ MA8 │ MA8 │
│ 3 │ DBO │ DBO │ 18 │ MA9 │ MA9 │
│ 4 │ MAO │ MAO │ 19 │ MA10│ RAS1 │
│ 5 │ MA1 │ MA1 │ 20 │ DBS │ DBS │
│ 6 │ DB1 │ DB1 │ 21 │ WE │ WE │
│ 7 │ MA2 │ MA2 │ 22 │ GND │ GND │
│ 8 │ MAZ │ MAZ │ 23 │ DBb │ DBb │
│ 9 │ GND │ GND │ 24 │ N.C.│ PrD │
│ │ │ │ │ │ (GND) │
│ 10 │ DB2 │ DB2 │ 25 │ DB7 │ DB7 │
│ 11 │ MACH │ MACH │ 26 │ DB8 │ PrD │
│ │ │ │ │ Out │ (1M=GND)│
│ 12 │ MAS │ MAS │ 27 │ RAS │ RAS │
│ 13 │ DBЗ │ DBЗ │ 28 │ CAS │ N.C. │
│ │ │ │ │Parity │
│ 14 │ MAb │ MAb │ 29 │ DB8 │ DB8 │
│ │ │ │ │ In │ In/Out │
│ 15 │ MA7 │ MA7 │ 30 │ +5V │ +5V │
└────┴─────┴─────┴────┴─────┴─────────┘STD - standard SIMM (SIPP)
IBM - IBM SIMM
Table 3.
Pin assignment of 72pin SIMM modules.
┌────┬──────┬────┬──────┬────┬──────┐
│Pin │ Name │Pin │ Name │Pin │ Name │
├────┼──────┼────┼──────┼────┼──────┤
│ 1 │ GND │ 25 │ DB22 │ 49 │ DB8 │
│ 2 │ DBO │ 26 │ DB7 │ 50 │ DB24 │
│ 3 │ DB16 │ 27 │ DB23 │ 51 │ DB9 │
│ 4 │ DB1 │ 28 │ MA7 │ 52 │ DB25 │
│ 5 │ DB17 │ 29 │ BSO │ 53 │ DB10 │
│ 6 │ DB2 │ 30 │ +5V │ 54 │ DB26 │
│ 7 │ DB18 │ 31 │ MA8 │ 55 │ DB11 │
│ 8 │ DBЗ │ 32 │ MA9 │ 56 │ DB27 │
│ 9 │ DB19 │ 33 │ RASЗ │ 57 │ DB12 │
│ 10 │ +5V │ 34 │ RAS2 │ 58 │ DB28 │
│ 11 │ CASp │ 35 │ DP2 │ 59 │ +5V │
│ 12 │ MAO │ 36 │ DPO │ 60 │ DB29 │
│ 13 │ MA1 │ 37 │ DP1 │ 61 │ DB13 │
│ 14 │ MA2 │ 38 │ DPЗ │ 62 │ DBЗO │
│ 15 │ MAZ │ 39 │ GND │ 63 │ DB14 │
│ 16 │ MACH │ 40 │ CASO │ 64 │ DBЗ1 │
│ 17 │ MAS │ 41 │ CAS2 │ 65 │ DB15 │
│ 18 │ MAb │ 42 │ CASЗ │ 66 │ BS2 │
│ 19 │ Rsv. │ 43 │ CAS1 │ 67 │ PDO │
│ 20 │ DBCH │ 44 │ RASO │ 68 │ PD1 │
│ 21 │ DB20 │ 45 │ RAS1 │ 69 │ PD2 │
│ 22 │ DBS │ 46 │ BS1 │ 70 │ PDЗ │
│ 23 │ DB21 │ 47 │ WE │ 71 │ BSЗ │
│ 24 │ DBb │ 48 │ Rsv. │ 72 │ GND │
└────┴──────┴────┴──────┴────┴──────┘
Designations:
PD - Presence Detect - identifieravailability and type.
N.C.- No Connection - free output.
DBi - data bits.
DB8 - parity bit for SIMMZO.
DPi - parity bit of the i-th byte.
MA - multiplexed address.
RAS, CAS - row and column sampling strobes
tsa accordingly.
WE - record.
BS - block sample.
Rsv - Reserved.
The article uses materials from M. Hooke's book "Hardware
IBM PC tools", publishing house "Peter Press", 1996.
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