Born Dead #05 06 января 1999

Amiga     Программирование

World Amiga - Amiga eyes RRA (Part 1).

                  AMIGA eyes>> RRA>> Part I


(C) 1998>> RRA>> / AF / SG


    What a fuck!!! After I filled my 20 kilos of text from
I zaglyuchil plume diskoflopa and all my writings have covered 
something soft and fluffy. Okay, I do not care, and the 
bladder, I should only a quarter of a devastated, so let's 
start all over again. Very sure that all of the above words 
will be censored aka Zaksor Unbel! Ever.



    In this series, I want to briefly explain and understand all
the main provisions of the programming on Amiga. In fact, I 
already filled article on the mechanism of exceptions and 
interrupts, but it turned out that quite a few people know 
assembler Ammi, and so still have all this horror to describe 
(the emphasis on the last syllable! :)).



    How can you be known to the Amiga CPU stand firm
Motorola (turns out they do not only pagers and mikruhi
for motor scooters). By the way, on most game consoles
are precisely their processors, such as well-known and Dandy
Sega, who seduced more than half the users Speccy. In this
article I will describe the addressing modes, data organization 
and begin detailed description of the command processor family 
MC680x0, which and stand on the Amiga. In subsequent articles I 
will detail all Amiga chipset. I want to send a big FUCK author 
of "AMIGA: Assembly programming, I do not remember how his last 
name, toli Mikhailov, Mihuylov toli, toli Mihuelovsky. From this

Books can only pull a list of library functions Amiga
DOS, the rest can be safely discarded. Catchphrase of this
Books: "... detailed information on hardware-register you will 
be able found in the technical documentation Amiga ...". I 
wonder where he is found it! Head of "attack" will contain full 
information about that I was thinking about this little book, 
and about its author. My stuff articles was assembled bit by 
bit from different sources, and by hacking known Break games 
"WALKER", and all other softiny. How does it already been made 
when talking about the Amiga parallel smear PC. By that I do I 
will not, and PC and Spectrum (to my deep Unfortunately they 
are relatives) will be used for comparison. 

So, iNTEL OUTSIDE!
Battle cry uttered start of our sheep:


                 Processor Family MC680x0


    This family is still quite extensive: MC68000, MC68EC000,
MC68HC000, MC68008, MC68010, MC68020, MC68EC020, MC68030,
MC68EC030, MC68040, MC68LC040, MC68EC040, MC68330, MC68340,
ustroistvo paged memory management and MC68851
math coprocessor MC68881, MC68882. Here I
will focus on processors that are on the Amiga: MC68000,
MC68020, MC68030, MC68040, MC68060, and some variations such as
MC68EC020.


    From this set of most different processor MC68000.
It has fewer addressing modes, command and control
registers. MC68000 stood on the Amiga chipset OSC and ESC.
Other processors on the instructions and registers in fact 
similar. Further, under the words "senior processors" I mean

processors older than the MC68000.


    All these processors operate in two modes:
nick (user) and the supervisor. In user mode, the processor is 
not have access to control registers and can not perform

team working with them (this leads to the exclusion of "breach 
of privilege ", more on this will be written later.) These modes

were introduced for multi-tasking systems. For example Workbench
operates in supervisor mode and has access to all resources
processor and all the Amiga in general, and correspondingly 
soft yuzersky operates on a user and can only perform all sorts 
of Computing and glitches especially without affecting the 
overall health of the Amiga. 


                    REGISTER IN USER MODE


    Data registers D0-D7 (32 bit): In them you can store
data and perform arithmetic on them all sorts of perverted. So
also used as index registers. The size of operations with these
registers: bit, bit field, B (. B), word (. W), long
word (. L), quadword (any 2 data register).


    Address registers A0-A7 (32 bits): used as an index
registers or registers base address. Size of operations
these registers: word and long word. Register A7 is used
as the stack pointer (SP - stack pointer). In the nick
user stack is used (USP - user SP) (all 3 in their senior
CPUs - USP, ISP, MSP, and 2 MC68000 - USP, SSP. see
next chapter). I hope that this explains the stack will not
required.


    Register PC (32 bits): this is not the PC, which suxx, but 
the which indicates the currently executing a command, so to 
speak program counter.



    Register CCR - condition code register (8 bits): one word
a register of flags, and with anglitskogo register code of (yx 
as zamorocheno). Honestly it's only 5 bits

more tricked register SR is fully accessible only in
supervisor mode (see the next. chapter).


    Bit 0: C - CARRY, carry flag. Set if the Loss
               zoshel transport high bit when adding or loan

               by subtracting (when I read in a book on

               Spectrum assembler, then I do not understand

               and by the way I know friends who have not yet

               know how it juzat although almost finished his

               prog). Also, this flag changes teams

               shift.

               Uses conditional branch commands.


    bit 1: V - OVERFLOW, overflow flag. Set,

               if arithmetic overflow occurred, then

               is to say the result does not fit the specified 
size. 


    Bit 2: Z - ZERO, zero flag. Lameroo clear that this flag

               set when the result is zero.


    bit 3: N - NEGATIVE, the sign flag. If the result is 
negative                LIMITED, a flag is set. In a word copy 
of the old                Sheha bit result.



    Bit 4: X - EXTEND. A copy of the flag C, although some of 
his team 

               in contrast to C is not affected. Used to

               arithmetic instructions and commands the shift.


    In the user registers are also available mathematical
coprocessor, but unfortunately I have absolutely no bychu in 
floating arithmetic, so nothing on this issue can not say.




                 REGISTERS in supervisor mode


    In addition to the above registers mode
Supervisor provides the following:

 Register A7 ', A7''- in principle it is the same A7, which was
user mode, only the values ​​in different modes is excellent. On
Senior processors, respectively, the main stack (MSP -
master stack) and stack interrupt (ISP - interrupt stack). The 
first cut one when you switch to supervisor mode, the second

if the interruption occurred (note: all interrupts and
exceptional work in the supervisor mode is not dependent on 
whether the what mode you were before. Exit mode

restored). On the MC68000 operates in supervisor mode
System Stack (SSP - system stack, rather than the supervisor 
stack, as It was said in the book, which I am sending a second 
fuck). 


    Register SR (status register): register of flags or register
status, call it what you want.


    Bits 0-4: Flags conditions. See register CCR.

    Bits 5-7: equal to 0.

    Bits 8-10: I0-I2 - Mask interrupt priority (ob'yasmyu

                later)

    Bit 11: 0.

    Bit 12: M - 0 = ISP

                    1 = MSP

    Bit 13: S - 0 = user mode

                    1 = supervisor mode

    Bits 14,15: T0, T1 - trace mode.



                T1 T0 Mode


                 0 0 no trace

                 1 0 trace of each team

                 0 1 only trace command branch

                       (Older processors)

                 January 1 don't work!


    Register VBR (vector base register) (older processors) -
contains the address of the interrupt vector table (to be chewed
later).


    Registers SFC / DFC (source / destination alternate function
code register) (older processors) - contain 3 bits, which
complete logical address. In consequence of this processor can
refer to 8, 4-gigabyte memory areas. Of course I
would like to have the Amiga with its 32 gigami, but it looks 
like problematic, so the use of these registers

impractical.


    Control registers actually quite a lot, here I am
listed the main ones. And now I will give a list of all control
registers and processors in which they live.

AC1, AC0 - ACCESS CONTROL REGISTER: 68EC030
ACUSR - ACCESS CONTROL UNIT STATUS REGISTER: 68EC030
CAAR - CACHE ADDRESS REGISTER: 68020,68 EC020, 68030,68 EC030.
CACR - CACHE CONTROL REGISTER: 68020,68 EC020, 68030,68 EC030,

          68040,68 EC040, 68LC040.

DACR0, DACR1 - DATA ACCESS CONTROL REGISTER: 68EC040
DTT0, DTT1 - DATA TRANSPARENT TRANSLATION: 68040,68 LC040.
IACR0, IACR1 - INSTRUCTION ACCESS CONTROL REGISTER: 68EC040
ITT0, ITT1 - INSTRUCTION TRANSPARENT TRANSLATION REGISTER:

              68040,68 LC040.

TT0, TT1 - TRANSPARENT TRANSLATION REGISTER: 68,030
CRP - CPU ROOT POINTER: 68,030
PMMUSR - PAGED MEMORY MANAGMENT UNIT STATUS REGISTER: 68030,

          68040,68 LC040.

MMUSR - MEMORY MANAGMENT UNIT STATUS REGISTER: 68030,68040,

        68LC040.

SRP - SUPERVISOR ROOT POINTER: 68030,68040,68 LC040.
TC - TRANSLATION CONTROL REGISTER: 68030,68040,68 LC040.
URP - USER ROOT POINTER: 68040,68 LC040.

There is common term transparent translation, I do not know
exactly how to translate this mustdie, but the sense I think I 
understand. Such registers are living in processors with 
built-in MMU (no confused with M.M.A. - The latter translates 
as local maniac Amiga, and the MMU is nothing but a memory 
managment unit, I mean memory management unit). So this is the 
translation pervodom is logical to physical address for

paging memory. Maybe I'm lying. As with
MMU I have experience of communication was not there. ACCESS 
CONTROL registers too involved in this incomprehensible 
process. Processors with built-in MMU - MC68030, MC68040, 
MC68LC040. 



                         Data Format


    These processors operate with the following data types:

bit 1 bit
bitfields 1-32 bit sequence of bits

                             (Older processors)
BCD-number of 8-bit Packaging: 2 numbers per byte

                             nepakovanoe: 1 number to the byte
byte 8 bits
16-bit word
long word with 32 bits
64-bit quadword any 2 data register
16-byte block of 128 bits of memory. The address is a multiple 
of 16. 

                             Only the CPU MC68040.


           ORGANIZATION OF DATA IN REGISTERS AND MEMORY


    The data in the registers are as follows:


                   31 0

    longword X X X X

    word. . X X

    bytes. . . X


    Data in memory located on the circuit big-endian, ie
significant byte at the lowest address. On a PC, and applied 
Spectrum'e scheme is little-endian, least significant byte at 
the lowest address. For example: number 12345678 in the memory 
will be located as follows: 

on the Amiga:


    address number


    1000 12

    1001 34

    1002 56

    1003 78

but on the PC and Spectrum'e:


    1000 78

    1001 56

    1002 34

    1003 12


    It seems that everything is clear.


                       Method of addressing


    This article will often meet such a thing as
effective address is <ea>, it refers to the address operand. 
For example data is in a cell with the address 500, <ea> operand

These data will be 500. Here I will address all yuttody
processor family MC680x0.

 1) Distinctive Software Data Register. Operand in register
data. Write in assembly language: Dn.

 2) The register address register software. Operand in register
address. Write in assembly language: An.

 3) INDIRECT Distinctive. <Ea> operand in register
address. Record in the assembler: (An)

 4) indirect Distinctive with post-increment. <Ea> operands
register addresses. After use, <ea> address register
incremented by 1,2 or 4 bytes depending on the size
operation (. B,. W or. L). Record in the assembler: (An) +.

 5) INDIRECT Distinctive C-decrement. Address register
decremented by 1,2 or 4 bytes depending on the size
operation (. B,. W or. L). <Ea> operand is in this case
address. Record in the assembly: - (An).

 6) Distinctive INDIRECT With 16-bit offset. <Ea> operand
is equal to the contents of the address register plus 16-bit 
signed offset. Write in assembly language: d16 (An).


 7) The register INDIRECT WITH INDEX AND 8-bit OFFSET.
<Ea> operand is the sum of the contents of the register 
address, sign 8-bit offset and scaling (* 1 * 2 * 4 or * 8)

index register (data register or address). Size
index register can be. W or. L. Write in assembly language:
d8 (An, Xn.size * scale).

 8) COMPLETE SHORT. <Ea> operand is given directly
pre-expansion to 32-bits, taking into account the sign. Record 
in Assembler: (xxx). W


 9) absolute length. <Ea> operand
directly. Write in assembly language: (xxx). L

 10) DIRECT. Operand is specified directly. Record
in assembly language: # xxx

 Other methods of addressing only work on older
processors.

 11) INDIRECT Distinctive With INDESKSOM and base offset.
<Ea> operand is the sum of the contents of the address 
register, the base the displacement and scaling the index 
register. All these parameters are optional. If neither option 
is not specified - <ea> 0. Write in assembly language: (bd, An, 
Xn.size * scale). 

 12) INDIRECT POSTINDEKSNAYA through memory. For the beginning 
is taken the number of addresses equal to the sum of basic 
offset and the contents address register. <Ea> operand is the 
sum of the numbers, scaled index register and an external

bias. All parameters are optional. Write in assembly language:
([Bd, An], Xn.size * scale, od).

 13) INDIRECT PREINDEKSNAYA through memory. For the beginning 
is taken number at the address equal to the sum of register 
contents address base offset, and scaling of the index

register. <Ea> operand is the sum of the number and appearance
bias. All these parameters are optional. Write in assembly 
language: ([Bd, An, Xn.size * scale], od).



    Addressing 6,7,11,12 and 13 can be used instead of the base
Programming of the address register counter PC.


    At the moment I have nothing else to say except
sent a third fuck author vysheopuschenoy books. In the next
article I will describe the whole (and perhaps not all) of the 
command system processors MC680x0. Good bye!


<--- ->

From the editor:

Anticipating all sorts of silly assaults declare themselves: 
this cycle Articles found it useful and interesting, not only 
for spektrumistov, but also for experienced amizhnikov. Come, 
comrades, time to get acquainted with other platforms closer, 
come! For those does anyone still do not understand fun to 
repeat that: the author no its Amigo, and most of the above 
Roma realized himself studying codes Amiga programs in their 
native ZX in a makeshift emulator / debugger. And this is only 
the beginning! Now>> RRA>> picking Sony PlayStation - ready 
same emulator. Only two of its characteristics: the memory is 
emulated by using 6 (Shesti!) floppy disks and caching, and one 
frame is generated around hour. And it's not funny!