Nicron #12 20 декабря 1996

Железо

Iron - an overview of the microprocessor Zilog Z380, continued.

                          MPU Z380

[Continued. Beginning in the rooms 11,10,9,8,7].

(C) WLODEK BLACK.

    Command group arithmetic basic purpose
    and a group of commands by the CPU.

New commands:

Mnemonic Meaning Commentary

CPLW HL <- NOT HL inversion pair HL, serving
CPLW HL as a 16-bit Batteries pa.

NEGW HL <- 0-HL sign change values ​​pair HL
NEGW HL

EXTS L <- A
EXTS AH <- 00 if the battery D7 = 0;
        H <- # FF, if - - = 1

                Expansion of 8-bit value
    battery life of up to 16 (or 32 bits in the "long term")
    bits with the transfer of the result in HL. Sign bit limit 
is formed in the importance of significant bits of the word. 

EXTSW HLz <- # 0000 for H (7) = 0;
EXTSW HL HLz <- # FFFF for H (7) = 1

                Extending the 16-bit values ​​of the HL to 32 
bits, taking into account the sign. 

SLP Sleep Translated chip processor
    economical mode shutdown. Terminate the generation of light 
pulses as built-in power, switch off the processor differs from 
the data bus and control; address bus translation tsya a logic 
1 state with an open drain; dramatically reduces the power 
consumption of the Xia. Exit Sleep can be reset by closing the 
pre masked and nonmaskable and a request for Zach watt system 
bus. If the transition to Sleep banned (? -     have not yet 
figured out how!), then the SLP is running as HALT. 

DI n IER (i) <- 0, in accordance with bits of n.
    SR (5) <- 0 if n (0) = 1.
    NeuStar mask bits in the register of the interrupt 
prohibition     Interrupt Enable. There are 4 significant bits 
(0 ... 3)     in the register IER (more will be covered in the 
study     interrupt mode).


EI n IER (i) <- 1 - - Similarly, to allow interrupts.
    SR (5) <- 1 - "-.

IM 3 Enabling third interrupt mode.

LDCTL SR, A SR (31-24) <- A initialization control register SR 
(23-16) <- A value of the battery.         SR (15-8) <- A


LDCTL SR, n Load Control same - a constant.
        SR (31-24) <- n
        SR (23-16) <- n
        SR (15-8) <- n

LDCTL HL, SR HL (15-0) <- SR (15-0) Reading registry control of 
a pair of HL. In the "longest word" read         32 bits.


LDCTL SR, HL SR (15-8) <- HL (15-8) Load control register SR 
(0) <- HL (0) leniya value pair HL.         SR (31-24) <- HL 
(15-8)         SR (23-16) <- HL (15-8)

        In the "long term":
        SR (31-16) <- HL (31-16)

LDCTL A, v A <- v Reading 8-bit group register
            Control SR in the battery. ("V" - a
            group YSR, XSR or DSR).

LDCTL v, A v <- A Load 8-bit groups Regis trajectory control 
value of SR Batteries pa. 

LDCTL v, nv <- n The same constant.

SET LCK SR (1) <- 1 set the lock requests
            to capture the system bus.

RESC LCK SR (1) <- 0 unlock - "-.

SETC LW SR (6) <- 1 Set Mode "long term"

RESC LW SR (6) <- 0 to lift the "long term".

BTEST Bank Test Storing some bits Regis S <- SR (16), spectrum 
management at the flags.         Z <- SR (24)

        V <- SR (0)
        C <- SR (8)

MTEST Mode Test Same, but with other bits for
        S <- SR (7), controlling for other states.
        Z <- SR (6)
        C <- SR (1)

[To be continued].