Nicron #10 05 декабря 1996

Железо

Iron - an overview of the microprocessor Zilog Z380, continued.

                          MPU Z380

[Continued. Previous publications - in rooms 9,8,7,6. ]

(C) WLODEK BLACK

... So we got to the command system! Let's start with the 
easiest, as usual, - shipments. 

        The Group commands an 8-bit boot.

It added to the existing instructions in the Z80 only
operations with the halves of the index registers:

Command Action

LD XYU, n XYU <- n
LD XYL, n XYL <- n

, Where "XY" - IX or IY, and "n" - 8-bit constant.

Also announced the team hops between the two halves of the index
registers and general purpose registers:

LD XYU, s
LD XYL, s
LD s, XYU
LD s, XYL

Where "s" - a general purpose register.

In fact, these operations were performed and Z80, but they were 
not declared on the official list of commands. Now they had the 
standard mnemonics, and with it the full entry in the list of 
instructions. 

Instructions form
LD r, (XY + d) LD (XY + d), r
LD (XY + d), n
LD A, (nn) LD (nn), A
can be prefiksovany DDIR IB or DDIR IW to enhance the bit 
operand. The rest of the group of 8-bit transfers is exactly 
the same as a prototype.


        Command group 16 - and 32-bit download.

New commands:

LD [W] (pp), nn (pp +1) <- nh load 16-bit constant nn
        (Pp) <- nl at the address indicated by a pair
                pp, for example, LD (BC), nn;

LD pp, (uu) pph <- (uu +1) Load Indirect register
        ppl <- (uu) pair pp to the address indicated
                pair uu, for example LD IX, (BC);

LD (pp), uu (pp +1) <- uuh placing value on a pair of uu
        (Pp) <- uul address indicated by a pair pp:
                LD (DE), IX;

LD pp, UU pp <- UU shipment value of one pair
                the other: LD BC, HL;

LD XY, pp XY <- pp LD IX, BC; LD IY, DE;
LD pp, XY pp <- XY LD BC, IX; LD DE, IY;

LD IX, IY shipment value of one
LD IY, IX index register to another;

LD (pp), XY (pp +1) <- XYU retention index register
        (Pp) <- XYL at the address indicated by a pair pp;
                LD (BC), IX;

LD XY, (pp) XYU <- (pp +1) load index register with the
        XYL <- (pp) addresses that you specify a pair of pp;
                LD IY, (DE);

LD pp, (XY + d) pph <- (XY + d) h loading pp pair from an 
address Indus ppl <- (XY + d) l ksiruemogo in IX or IY with 
mixed generalization of d: LD HL, (IX + d ); 

LD IX, (IY + d) loading a single index regiLD IY, (IX + d) 
countries to address, indexed                 other index 
register by                 displacement d;


LD pp, (SP + d) pph <- (SP + d) h load with a pair of 
addresses, the index of ppl <- (SP + d) l orientable stack 
pointer SP with                 displacement d; LD DE, (SP + d);


LD XY, (SP + d) - "- index register;

LD (XY + d), pp loading in the opposite naLD (IX + d), IY board 
- putting a pair of pp LD (IY + d), IX or the index register in 
memory LD (SP + d), pp address, indexed or XY

LD (SP + d), XY SP;

LD [W] I, HL I <- HL load register interrupt vector vany value 
pair HL;                 LD I, HL; LDW I, HL ("W" - not neces 
sarily element); 

LD [W] HL, I HL <- I read interrupt vector register states in a 
pair of HL;                 LD HL, I; LDW HL, I.


Symbol "W" can be used for ease of reading programs, to 
visually emphasize that we are talking about operand format 
"Word". 

All teams for 16-bit download, including "old" in the "longest 
word" (LW; Long Word mode), set in the register SR, will work 
with 32-bit operands. A one-byte offset into the index 
operations, and 16-bit address operations with direct 
addressing can be extended to respectively 16 or 24-bit or 
24-bits or 32 bits using a prefix DDIR IB, DDIR IW, if the data 
format is set to single word. In the "long word operands are" 
16-bit address " and so turn into 32-bit and require a 
corresponding number of bytes, but the index offset remains in 
the same format and requires, if necessary, prefiksovaniya DDIR 
(! Perhaps This nuance something I messed up and (still to read 
the English original)). 

            Group PUSH / POP.

Posted by:

PUSH nn (SP-2) <- nnl entering the stack constant;
        (SP-1) <- nnh (constant can be expanded
        SP <- SP-2 through DDIR);

PUSH SR (SP-2) <- SR (7-0)
        (SP-1) <- SR (15-8)
        SP <- SP-2

POP SR SR (6-0) <- (SP) <- bits of SR (7) do not intersect SR 
(15-8) <- (SP +1) is set by         SR (23-16) <- (SP +1) POP; 
a bit extended SR (31-24) <- (SP +1) Nogo processor mode;       
  SP <- SP +2 you can reset it only to the RESET-om; 

With an established format "common word" POP SR, as seen, it 
behaves quite original - 8 ... 15-th bits are copied to SR 2 
high byte register. Under the regime of "long term" in the 
stack is stored all 32-bit value and so are all removed at POP 
(this holds for all register pairs); upper half 32-bit value is 
stored on the stack first (with respect to the "core" of 
values). "PUSH nn" can be expanded using DDIR. Unexpanded "PUSH 
nn" in the "long term" puts an additional # 0000 in the stack 
(as it relates to the PUSH AF). "POP nn", of course, there is 
no (obvious meaning). When the processor in a mode of "Z80" 
stack pointer looped for Junior 64K memory; significant bits 
set to 0. 

[To be continued].