Nicron #07
14 ноября 1996 |
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Iron - an overview of the microprocessor Zilog Z380, continued.
MPU Z380 (C) WLODEK BLACK Microprocessor Z380. Continued. Beginning in room 6. Hello again, friends! Nice to know that your work benefits. Already received the first response - enthusiastic, I must say! And indeed, this chip that is worthy. Zaglyanemka that he was inside? .. Yeah, everything seems to be familiar: the battery, and flags, HL, DE, BC, the index registers IX and IY, the pointer stack, program counter, register regeneration RAM R, register interrupt vectors I. .. Here is a map register space, which I reproduce symbols pseudographics, defiantly expanding its three-dimensionality to the left (in the original - right): A F BCz B C DEz D E HLz H L IXz IXU IYU IYz IYU IYL A 'F' BCz 'B' C ' DEz 'D' E ' HLz 'H' L ' IXz 'IXU' IYU ' IYz 'IYU' IYL ' R Iz I SPz SP PCz PC As you can see, a set of general-purpose registers (GPR) looks pretty familiar. The difference with the Z80 is that in each of two sets - the mainstream and alternative - a quadruple set similar to appoint Ron, and enhanced registers to 32 bits. RON is used for storing and processing data and for addressing memory, and restrictions on the ways of addressing a 380-th significantly less. Treatment of RON defined in the codes of commands plus the active register slot is given by bits of the control register SR. Note: halves, index registers appeared official mnemonics - IXU, IYU for older halves and IXL, IYL for the youngest. (Offer in the manner of delusion: it can take into account appeared in the new standard and assembler for Z80, support mnemonics like "LD LX, E"?). Not hard to guess that suffix "z" denotes the union of the register line in 32-bit register, but only in the descriptions, but not in mnemonic operations. Control register SR. <------------ YSR ------------> <------------- XSR -------- -> 0 0 0 0 0 IY bank IYP 0 0 0 0 0 IX bank IXP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 <--------- DSR --------------> Main IEF 0 0 0 0 0 Bank Alt XM LW 1 IM 0 LCK AFP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IYBANK - 2-bit field select bank IY-registers. Contains a number (0 ... 3) the bank or IY IY '. After RESET is reset to 0. IYP - bit of a choice of primary or alternate block registers IY. 0 - the core set, 1 - an alternative set. IXBANK, IXP - the same for the IX. MAINBANK - 2-bit field selection unit registers AF, HL, DE, BC and A ', F', HL ', DE', BC '. Contains the number of register bank. ALT - bit of a choice of primary or alternative set of HL, DE, BC. 0 - primary, 1 - alternative. XM (Extended Mode) - bits set the operation mode of the processor. 1 - Advanced mode 0 - mode Z80. Switch back to 0 not (only RESET; even POP does not help). LW (Long Word mode) - bit control mode ", the word" / "long term". 1 - a long word, 0 - normal (16-bit) word. (For single instruction can be set individually mode word length, operating only within one team, with special teams). RESET resets to 0. IEF1 - flag permits maskable interrupts. 1 - Interrupt allowed, 0 - interrupt disabled. RESET resets to 0. IM - 2-bit field mode interrupt 0,1,2 or 3. LCK (Lock) - lock-bit service requests to access the system bus by other devices. 1 - external requests ignored, 0 - external requests are serviced. RESET resets to 0. AFP - bit of a choice of primary or alternate block registers AF (AF or AF '). 0 - primary, 1 - alternative. Register SR software is available as a 32-bit SR, such as 3 eight-bit register YSR, XSR and DSR, and can also be saved through PUSH and downloaded via POP. (To be continued).
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