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The ZX-SPECTRUM 48 & 128 computers
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Extended devices and user's manual
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(c) UAЗPRQ/Borisov Serge
продолжение
Буфер шины адреса CPU Z80:
К555АПб К555АПб
┌───┬────┬───┐ ┌───┬────┬───┐
2 │ │ BD │ │18 2 │ │ BD │ │18
A0 ────┤A0 │ │B0 ├────> A0' A8 ────┤A0 │ │B0 ├────> A8'
│ │ │ │ │ │ │ │
.. ... │.. │ │.. │ ... .. .. ... │.. │ │.. │ ... ..
9 │ │ │ │11 9 │ │ │ │11
A7 ────┤A7 │ │B2 ├────> A7' A15────┤A7 │ │B2 ├────> A15'
│ │ ││ │ │ │ │
├───┤ ├───┤ ├───┤ ├───┤
1 │ │ │ │20 1 │ │ │ │20
+5V────┤A/B│ │Ucc├───> +5V +5V ────┤A/B│ │Ucc├────> +5V
9 │ ─ │ │ │10 9 │ ─ │ │ │10
┌──┤EO │ │GND├───┐ ┌──┤EO │ │GND├───┐
│ │ │ │ │ │ │ │ │ │ │ │
▀▀▀ └───┴────┴───┘ ▀▀▀ ▀▀▀ └───┴────┴───┘ ▀▀▀
The sign (') marks the output signals, which will be further
must be used to connect peripherals.
Similarly, it is advisable to buffer signals
Z80 controls:
K555APb
┌───┬─────┬───┐
── 2 │ │ BD │ │18 ──
Z .. RD ────────┤A0 │ │B0 ├───────> RD'
X ── 3 │ │ │ │17 ──
WR ────────┤A1 │ │B1 ├───────> WR'
S ─── 4 │ │ │ │16 ───
P OIRQ* ────────┤A2 │ │B2 ├───────> OIRQ*'
E 5 │ │ │ │15
C CLK 3.5 ───────┤A3 │ │B3 ├───────> 3.5' Mhz
T 6 │ │ │ │14
R CLK 2.0 ───────┤A4 │ │B4 ├───────> 2.0' Mhz
U 7 │ │ │ │13
M CLK 1.75 ──────┤A5 │ │B5 ├───────> 1.75' Mhz
───── 8 ││ │ │12 ─────
RESET ───────┤A6 │ │B6 ├───────> RESET'
9 │ │ │ │11
reserve ───────┤A7 │ │B7 ├───────>
│ │ │ │
├───┤ ├───┤
1 │ │ │ │20
+5V ────────┤A/B│ │Ucc├────> +5V
9 │ ─ │ │ │10
┌────┤EO │ │GND├────┐
│ │ │ │ │ │
▀▀▀ └───┴─────┴───┘ ▀▀▀
It is advisable to install the data bus buffer on the socket, because at
in experiments it is often he who becomes the “victim”. SD buffer
automatically disconnects from the bus when accessed by a computer
(read/write) to ports #7B, #FB and #FE. In 128K computers port
#XXFD is still not controlled by this scheme, however, when
accessing music coprocessor registers (read/write)
everything happens correctly, because AY connects via buffer; at
accessing the RAM-DISK (#7FFD) only writes to
this port and, in principle, it does not matter that the buffer passes data
through yourself. In processor maskable interrupt mode (IMO,IM2)
even if the addresses A0=1, A2=1 match, the IORQ signal
will be activated, which removes the SD buffer from the Z-state, however
inactive RD signal in Z80 interrupt acknowledge cycle
switches buffer directionin such a way that to the CPU bus it
connected by inputs. This way the buffer does not change state
bus and in the absence of an active device on it in the cycle
interrupt confirmation vector read by the processor is not
changes and in ZX-SPECTRUM without connected INTERFACE-1 is equal
#FF. Because such a device is more than rare in
in our country, it is not recommended to change the vector in hardware
interrupts (except those specially designed for this mode
devices) because it will make programs inoperable,
using IMO, IM2 mode. Application in computer
programmable parallel LSI adapter KPS8OBB55(A)
significantly expands the further operation of the machine and allows
the user will not have to worry about the connection in the future "not very
fast" devices running in parallel code
(printers, ADC, DAC, microcircuit diagnostic devices, programmer
etc.). Software support via the port simplifies the interface and
makes it more compact. If there is still a need for
using several similar ports simultaneously (eg.
in the advanced ROM programmer) it is advisable to connect via
system bus, because the number of connecting connections is reduced
wires, and use internal signals CHANNEL-0,..,5 for
CS of these devices.
to be continued...
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