Iron - Pentagon 2.666

 Pentagon 2.666                          
 King of Evil                           
                                                                
The main version currently supported by me is 2.6bbLE. In it 
the following has been implemented:                                          
                                                                
The main FPGA is EP2C8Q208C8 - Altera, Cyclone-II family.   
Total logical volume - 8256 macrocells ("logic elements" according to   
terminology f. Altera). As of today, 6017 are occupied.  
The distribution is as follows: 2623 occupies the Z80 code, 429+444 occupies 2  
YM2149 chip and digital channel adder (Turbo Sound, but there is   
the idea to combine their logical functions into one module), 305 -     
emulator VG93 (currently not fully debugged), 327 -     
video controller (displaying a standard       
ZX-screen and mode 1bCOLOUR), 75 - transparent text mode    
(displaying text on a VGA monitor on top of a regular ZX screen,  
used in the hardware debugger to display service        
information), 1814 - everything else (implementation                   
Spectrum-compatible architecture, memory mannep, work with       
peripheralmicrocontroller, hardware debugger, SD card and 
other little things that don't give a damn). The compiler is configured  
for maximum compilation speed to the detriment of the final logical 
capacity (the firmware is assembled from 12 to 30 minutes, depending on
settings (PC P4 2.8 Ghz, 4 Gb RAM, winXP 32 bit system,      
SPЗ)). At work it takes 3..6 minutes to assemble, computer 4 cores x 2.4    
Ghz, 4 Gb RAM, same system.                                   
                                                                
Video output - hardware implemented VGA, 50 Hz (others are possible       
frequencies), 5 bits for each color (!!!) independently.                
                                                                
Sound output - 2 channels x 8 bits independently.                   
                                                                
RAM - 2 MB SRAM. Minimum access time 10 ns 
(equivalent to 100 MHz sampling rate). In this case, 2 lines of 1 each 
MB, samples from which can be made independently (real        
the width of the SRAM data bus is 16 bits), but the real address bus 
chips are parallelized (saving FPGA pins).                     
                                                                
Peripheral controller - LPC2368FBD100 (ARM7TDMI, 512kb        
flash memory, 58 kb RAM, clock frequency 72 MHz (!!!)). Besides 
standard cases (RTC,ps2, timer, counter, SPI, i2c), can     
make a USB device (software update is supported in 2.6bble   
firmware via USB) and ethernet at the hardware level. In 2.6bble     
ethernet is not physically supported, but there is a connector on the board where  
you can connect a physical level (one chip, the output of which        
standard RG-45). In 2.666 without LE ethernet is physically available, but  
not through the hardware capabilities of the peripheral controller, but    
via a separate RTL8019 chip connected to external buses       
peripheral controller. There is no software (and there won’t be, judging by       
everything).                                                         
                                                                
In addition, the 2.6bbLe implements an ADC based on a peripheral      
controller (10 bits, sampling frequency ~100 kHz, a little more can be
lift). There is an SD card interface, IDE. No drive interface
(and there won’t be, due to its uselessness). But there is hope that I   
I’ll still add the VG93 hardware emulator.