Born Dead #07
12 марта 1999 |
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World Amiga - Amiga eyes RRA (Part 3): Basic Commands.
WORLD Amigo. PART III (C) 1999>> RRA>> / AF / SG (Continued in rooms 5 and 6) MAJOR COMMANDS -------------------------------------------------- ------------- ABCD - decimal addition in view of the flag X. Operation: DST = SRC10 + DST10 + X Syntax: ABCD Dy, Dx ABCD - (Ay), - (Ay) others addressing is not possible. Size:. B Description: Packaging adds two BCD-numbers and the flag of X. Flags: C, X - change N, V - indefinitely Z - 0, if the result is not 0, otherwise changes (!). For a correct determination this flag, before surgery, it should be install. -------------------------------------------------- ------------- ADD, ADDA, ADDI, ADDQ - addition Operation: DST = DST + SRC Syntax: ADD <ea>, Dn ADD Dn, <ea> ADDA <ea>, An ADDI # , <ea> ADDQ # , <ea> Size: ADD, ADDI, ADDQ -. B,. W,. L ADDA -. W,. L Description: ADD - addition of the data register with the operand in <ea> or vice versa. ADDA - register address + operand of <ea> ADDI - operand in <ea> + immediate data (That is any number). Impossible addressing modes: An ADDQ - in operand <ea + a number from 1 to 8. Flags: change everything except a team ADDA. It does not affect the flags. -------------------------------------------------- ------------- ADDX - taking into account the addition of a flag X Operation: DST = SRC + DST + X Syntax: ADDX Dy, Dx ADDX - (Ay), - (Ay) others addressing is not possible. Size:. B,. W,. L Description: Adds two numbers and the flag of X. Flags: C, X - change N, V - indefinitely Z - 0, if the result is not 0, otherwise changes (!). For a correct determination this flag, before surgery, it should be install. -------------------------------------------------- ------------- AND, ANDI - logical AND Operation: DST = DST'SRC Syntax: AND <ea>, Dn AND Dn, <ea> ANDI # , <ea> Size:. B,. W,. L Description: AND - performs AND operation on the register data and operand in <ea>. ANDI - logical operations on operands in <Ea>, and direct data. Addressing the forbidden: An Flags: X - does not change V, C = 0 N, Z - change -------------------------------------------------- ------------- ANDI to CCR - logical AND with the register of flags Operation: CCR = CCR'SRC Syntax: ANDI # , CCR Size:. B Description: The logical AND of the flags register, and directly governmental data. Flags: command performed on them. -------------------------------------------------- ------------- ASL, ASR - arithmetic shift left / right Operation: DST = DST SRC shifted again. Syntax: ASd Dx, Dy ASd # , Dy ASd <ea> Where d - the direction of the shift (L / R). Size:. B,. W,. L Description: arithmetic shift DST in a certain direction lenii. Flags C, X take the last extended bits. Counter the shift can be specified in two ways: 1) from 1 to 8 2) in the data register The team works with memory (ASd <ea>) produ leads to a shift 1 bit operand size only. W <Ea> can not be addressing: Dn, An ASL: multiplication by 2 in the degree of SRC C, X <operand <0 ASR: the division with a sign at 2 in the degree of SRC -> MSB Operand> C, X Flags: C, X - the last bit extended N, Z - vary depending on the result V - 1, if there was a change in sign -------------------------------------------------- ------------- Bcc - conditional branch Operation: if the condition is true, PC = PC + disp Syntax: Bcc <label> Size: offset can be as large. B,. W,. L . L - only on older processors. Description: If the condition is true, the execution of prog FRAMEWORK continues at PC + displacement. To model element of the command PC is at the team 2 CONDITIONS: BHI - more C = 0, Z = 0 BLS - less than or equal to C = 1 OR Z = 1 BCC - no transfer of C = 0 BCS - the transfer of C = 1 BNE - is not equal to Z = 0 BEQ - equal to Z = 1 BVC - no overflow V = 0 BVS - overflow V = 1 BPL - plus N = 0 BMI - minus the N = 1 BGE - greater than or equal to Z = 1 OR N = V BLT - less than N <> V BGT - more N, V = 1, Z = 0 OR N, V, Z = 0 BLE - less than or equal to Z = 1 OR N <> V Flags: do not change -------------------------------------------------- ------------- WARNING! Operation with bits FIRST Tests, a then already affect the specified bits. And he is not the result of the operation flags changes. BCHG - test and inversion of bits Operation: Z = test result bit bits = Z Syntax: BCHG Dn, <ea> BCHG # , <ea> Size:. B,. L Description: The Z flag is set in accordance with the test specified bits, then this bit is inverted. If the operation takes place on the register data, size of the operation -. L, the bit number given by the number from 0 to 31. If the team operates with a memory size of the operation -. B, the bit number from 0 to 7. The bit number can be specified in two ways: 1) directly 2) in the data register Addressing the forbidden: An Flags: Z - changes as a result of the test bit C, X, N, V - no change -------------------------------------------------- ------------- BCLR - Bit test and cleaning Operation: Z = test result bit bit = 0 Syntax: BCLR Dn, <ea> BCLR # , <ea> Size:. B,. L Description: The Z flag is set in accordance with the test specified bits, then this bit becomes zero. If the operation takes place on the register data, size of the operation -. L, the bit number given by the number from 0 to 31. If the team operates with a memory size of the operation -. B, the bit number from 0 to 7. The bit number can be specified in two ways: 1) directly 2) in the data register Addressing the forbidden: An Flags: Z - changes as a result of the test bit C, X, N, V - no change -------------------------------------------------- ------------- BFCHG - test and the inversion of the bit field (the elder processor) Operation: N, Z = result of the test field= neg Syntax: BFCHG <ea> {offset: width} Description: The tests and then inverts the bit field. Offset parameter specifies the starting bit of the field, and parameter width number of bits in the field. Addressing the forbidden: An, (An )+,-( An) Flags: X - do not change C, V = 0 N - a sign of the field Z - 1, all bits of the field equal to 0. -------------------------------------------------- ------------- BFCLR - testing and cleaning a bit field (the elder processor) Operation: N, Z = result of the test field = 0 Syntax: BFCLR <ea> {offset: width} Description: test, and then annihilate the bit field. Offset parameter specifies the starting bit of the field, and parameter width number of bits in the field. Addressing the forbidden: An, (An )+,-( An) Flags: X - do not change C, V = 0 N - a sign of the field Z - 1, all bits of the field equal to 0. -------------------------------------------------- ------------- BFEXTS - extract a bit field with the sign (SENIOR percent). Operation: Dn = Syntax: BFEXTS <ea> {offset: width}, Dn Description: Retrieves a bit field, adds a sign to 32-bit and adds to the specified data register. Test field also takes place. Offset parameter specifies the starting bit of the field, and parameter width number of bits in the field. Addressing the forbidden: An, (An )+,-( An). Flags: X - do not change C, V = 0 N - a sign of the field Z - 1, all bits of the field equal to 0. -------------------------------------------------- ------------- BFEXTU - extract a bit field unsigned (SENIOR percent). Operation: Dn = Syntax: BFEXTU <ea> {offset: width}, Dn Description: Retrieves a bit field, adds zeros to 32-bit and adds to the specified data register. Test field also takes place. Offset parameter specifies the starting bit of the field, and parameter width number of bits in the field. Addressing the forbidden: An, (An )+,-( An). Flags: X - do not change C, V = 0 N - a sign of the field Z - 1, all bits of the field equal to 0. -------------------------------------------------- ------------- BFFFO - search for the first unit in the bit field (SENIOR percent). Operation: Dn = Syntax: BFFFO <ea> {offset: width}, Dn Description: Looking for a bit field the most senior unit. For those who do not understand, for example: bitfield 001010110 ^ here it is In the case of data recorded number of the detected bit (Bit offset given in the command plus shift a bit in the field). If the bit is not found, is to say a bit field to 0 in the data register recorded bit offset given in the command plus the number of bits in the field. Offset parameter specifies the starting bit of the field, and parameter width number of bits in the field. Addressing the forbidden: An, (An )+,-( An). Flags: X - do not change C, V = 0 N - a sign of the field Z - 1, all bits of the field equal to 0. -------------------------------------------------- ------------- BFINS - insert a bit field. (SENIOR percent). Operation: = Dn Syntax: BFINS Dn, <ea> {offset, width} Description: Inserts a bit field, which is taken from the junior bits of the specified data register. For example: BFINS SRC, DST {5,4} DST: 0110 | xxxx | 01101 ^ SRC: 110100101 | xxxx | Offset parameter specifies the starting bit of the field, and parameter width number of bits in the field. Addressing the forbidden: An, (An )+,-( An) Flags: X - do not change C, V = 0 N - a sign of the field Z - 1, all bits of the field equal to 0. -------------------------------------------------- ------------- BFSET - test and set a bit field (SENIOR percent). Operation: N, Z = result of the test field = 1 Syntax: BFSET <ea> {offset: width} Description: test, and then fills in bit units field. Offset parameter specifies the starting bit of the field, and parameter width number of bits in the field. Addressing the forbidden: An, (An )+,-( An) Flags: X - do not change C, V = 0 N - a sign of the field Z - 1, all bits of the field equal to 0. -------------------------------------------------- ------------- BFTST - Test bit field (SENIOR percent). Operation: N, Z = result of the test field Syntax: BFTST <ea> {offset: width} Description: testing the bit field. Offset parameter specifies the starting bit of the field, and parameter width number of bits in the field. Addressing the forbidden: An, (An )+,-( An). Flags: X - do not change C, V = 0 N - a sign of the field Z - 1, all bits of the field equal to 0. -------------------------------------------------- ------------- BRA - unconditional branching. Operation: PC = PC + disp Syntax: BRA <label> Size: offset can be as large. B,. W,. L . L - only on older processors. Description: The program execution continues at PC + offset. At the time of the command PC is at Team 2. Flags: unaffected. -------------------------------------------------- ------------- BSET - Test and set bits. Operation: Z = test result bit bit = 1 Syntax: BSET Dn, <ea> BSET # , <ea> Size:. B,. L Description: The Z flag is set in accordance with the test specified bits, then this bit is set per unit. If the operation takes place on the register data, size of the operation -. L, the bit number given by the number from 0 to 31. If the team operates with a memory size of the operation -. B, the bit number from 0 to 7. The bit number can be specified in two ways: 1) directly 2) in the data register Addressing the forbidden: An Flags: Z - changes as a result of the test bit C, X, N, V - no change -------------------------------------------------- ------------- BSR - subroutine call. Operation: SP = SP-4 (SP) = PC PC = PC + disp Syntax: BSR <label> Size: offset can be as large. B,. W,. L . L - only on older processors. Description: Pushes onto the stack address of the next command, and then program execution continues at PC + offset. At the time of the command PC is at Team 2. Flags: unaffected. -------------------------------------------------- ------------- BTST - test bits. Operation: Z = test result bit Syntax: BTST Dn, <ea> BTST # , <ea> Size:. B,. L Description: The Z flag is set in accordance with the test specified bits. If the operation takes place on the register data, size of the operation -. L, the bit number given by the number from 0 to 31. If the team operates with a memory size of the operation -. B, the bit number from 0 to 7. The bit number can be specified in two ways: 1) directly 2) in the data register Addressing the forbidden: An. Flags: Z - changes as a result of the test bit C, X, N, V - no change -------------------------------------------------- ------------- CALLM - call module (only in 68020) Syntax: CALLM # , <ea> Description: <ea> is the address of the descriptor of the external modulation la. Frame of the module is created on top of the stack. Status of current module is saved in this frame. Operand # specifies the size (in bytes) arguments which are passed to the called module. Status of the new module is loaded from descriptor at <ea>. This team lives only on the processor M68020. It looks like the developers of processors MC680x0, not consider it necessary to use the commands to work with modules in the following processors, so use this command, I do not recommend. Flags: unaffected. -------------------------------------------------- ------------- CAS, CAS2 - compare and exchange (SENIOR percent). Syntax: CAS Dc, Du, <ea> CAS2 Dc1: Dc2, Du1: Du2, (Rn1): (Rn2) Size: CAS -. B,. W,. L CAS2 -. W,. L Description: The CAS compares operand of <ea> to the operand House Dc. If the operands are equal, then the write command Vaeth operand Du a <ea>, otherwise the operand of the <ea> a written in Dc. Prohibition of addressing: Dn, An Team CAS2 compares memory operand (Rn1) with operand Dc1. If the operands are equal, then comparands (Rn2) and Dc2. If these operands are equal, the operands and Du1 Du2 written in (Rn1) and (Rn2), respectively, other operands (Rn1) and (Rn2) recorded in Dc1 and Dc2. Rn1 and Rn2 - data registers or addresses that contain the address operands in memory. Flags: X - does not change N, Z, V, C - changed -------------------------------------------------- ------------- CHK - check register values to belong to a given range of numbers. Syntax: CHK <ea>, Dn Size:. W,. L (. L only on older processors) Description: Compares the number of data register with zero and operand given in the <ea>. If this number is less zero or greater than the upper limit (a <ea>), then exception occurs commands CHK, CHK2 (vector 6) Prohibition of addressing: An Flags: X - does not change N - 1 if Dn <0 0 if Dn> operands <ea> otherwise undefined. Z, V, C - undefined. -------------------------------------------------- ------------- CHK2 - check the value of the registry belonging to the set nomu range of numbers. (SENIOR percent). Syntax: CHK2 <ea>, Rn Size:. B,. W,. L Description: Sranivaet Rn for two boundaries. At <ea> are lower, then upper limits. Borders - signed numbers. If Rn is an address register, and the size operations. B or. W is the boundary in comparison extend the sign to 32 bits. If the register value lower than the or more of the top, then an exception occurs instruction CHK, CHK2 (vector 6). Prohibition of addressing: Dn, An, (An )+,-( An) Flags: X - does not change N, V - undefined Z - 1, Rn is a boundary C - 1, Rn out of bounds -------------------------------------------------- ------------- CLR - clear the operand. Operation: DST = 0 Syntax: CLR <ea> Size:. B,. W,. L Description: Though I will say everything is clear: the team annihilate operand of the <ea>. Prohibition of addressing: An Flags: X - does not change N, V, C = 0 Z = 1 -------------------------------------------------- ------------- CMP, CMPA, CMPI - a comparison. Operation: flags = DST-SRC Syntax: CMP <ea>, Dn CMPA <ea>, An CMPI # , <ea> Size: CMP, CMPI -. B,. W,. L CMPA -. W,. L Description: Comparison of going through the subtraction of the SRC DST (DST does not spoil). Flags are set in Under this subtraction. CMP - compare the data register with the operand in <Ea> CMPA - a comparison address register with the operand in <Ea> CMPI - a comparison in operand <ea> to direct governmental data. Addressing the forbidden: the team can not use the CMPI An. Use the address from register PC permitted. In the instructions CMP and CMPA can be used vat all kinds of addressing. Flags: X - does not change N, Z, V, C - changed -------------------------------------------------- ------------- CMPM - a comparison of memory Syntax: CMPM (Ay) +, (Ax) + Size:. B,. W,. L Description: Comparison of two memory locations whose addresses set in two registers addresses. The team always uses postinkrementnuyu addressing, that is to say after comparing both registers incremented on 1,2 or 4 bytes depending on the size operation. Flags: X - does not change N, Z, V, C - changed -------------------------------------------------- ------------- CMP2 - compare register with the boundaries (SENIOR percent). Syntax: CMP2 <ea>, Rn Size:. B,. W,. L Description: Sranivaet Rn for two boundaries. At <ea> are lower, then upper limits. Borders - signed numbers. If Rn is an address register, and the size operations. B or. W is the boundary in comparison extend the sign to 32 bits. This command is very similar to CHK2, the only difference is that the command does not cause exceptions. Prohibition of addressing: Dn, An, (An )+,-( An) Flags: X - does not change N, V - undefined Z - 1, Rn is a boundary C - 1, Rn out of bounds -------------------------------------------------- ------------- DBcc - check the condition, decrement and branching Syntax: DBcc Dn, <label> Size:. W Description: The command is designed for looping. For start command checks the flags, if the condition specified in the command is true, then the cycle is interrupted. (In DBF team out there on the condition, because condition is not always true). If the condition is not true a 16-bit counter is decremented Dn. If the counter is not equal to -1 (# FFFF), it is branching to <label>, otherwise the cycle interrupted. Address given by 16-bit offset from the PC. At the time of the command PC is at the team 2. Assemblers understand and mnemonic DBRA - the same as DBF. CONDITIONS: DBF or DBRA - FALSE DBT - TRUE DBHI - more C = 0, Z = 0 DBLS - less than or equal to C = 1 OR Z = 1 DBCC - no transfer of C = 0 DBCS - Transfer of C = 1 DBNE - is not equal to Z = 0 DBEQ - equal to Z = 1 DBVC - no overflow V = 0 DBVS - overflow V = 1 DBPL - plus N = 0 DBMI - minus the N = 1 DBGE - greater than or equal to Z = 1 OR N = V DBLT - less than N <> V DBGT - more N, V = 1, Z = 0 OR N, V, Z = 0 DBLE - less than or equal to Z = 1 OR N <> V Flags: do not change -------------------------------------------------- ------------- DIVS, DIVSL - the division of the sign Syntax: DIVS.W <ea>, Dn 16r/16q = 32/16 rest only on older processors DIVS.L <ea>, Dq 32q = 32/32 DIVS.L <ea>, Dr: Dq 32r/32q = 64/32 DIVSL.L <ea>, Dr: Dq 32r/32q = 32/32 Where q - quotient, r - balance Size:. W,. L Description: Performs the division with a sign. The team may have four types: 1) DIVS.W <ea>, Dn Dn divides a long word for word in <ea>. Quotient is placed in the low word register Dn, balance of age or older. The sign of the remainder is the same as a dividend. 2) DIVS.L <ea>, Dq Dq divides a long word for longest word in <ea>. The result of a 32-bit particular, they are not counted. 3) DIVS.L <ea>, Dr: Dq divides quadword Dr: Dq on the longest word in <ea>. 32-bit quotient placed schaetsya in Dq, 32-bit remainder in Dr. 4) DIVSL.L <ea>, Dr: Dq Dq divides a long word for longest word in <ea>. 32-bit quotient placed schaetsya in Dq, 32-bit remainder in Dr. When you divide by zero generates the Related exception. If the team has identified an overflow, it establishes logger flag V, and the operands are not changed. Flags: X - does not change C = 0 N, Z - vary according to private. undefined division by 0 and transition complement. V - 1, on overflow. Uncertainty in the fission to 0. -------------------------------------------------- ------------- DIVU, DIVUL - divide unsigned As DIVS, DIVSL only unsigned. About this team look a little higher. (To be continued)
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