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Nicron #16
17 января 1997 |
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Programming - a course of study assembler Wlodek Black, continued.
z80
[Continued].
(C) WLODEK BLACK
3 types of interrupts.
Interruption, which we have been discussing is, strictly
speaking, are called maskable hardware. Hardware - because it
caused by manipulating the electric signal. Masked - because
they can disable the software. It is logical to ask: it turns
out, there are no hardware interrupts and not masked? Answer:
Yes, there are. The former are called program, while the latter
are called Non-maskable. We'll talk about them later. Hardware
interrupts masked by their properties and character processing
are classified into 3 types, identified by numbers 0, 1 and 2.
Type 1 is the easiest. After receiving an interrupt, the
processor sends a return address stack and moves to address
0038h. That's all. With this address should begin interrupt
service routine. Type 1 interrupt in the system adopted for the
MSX standard. In All BIOS-ROM and included in the 0-th page of
memory addresses 0000h ... 3FFFh, from the address 0038h is the
same procedure interrupt handling. In the configuration of MSX
DOS on this site is located RAM, and it is placed at 0038h jump
to the address inside the JP MSX DOS, which in turn caused
BIOS. At the Spectrum in the range of addresses # 0000 ... #
3FFF always ROMs (one of three - BASIC-48, -128, TR-DOS), and
they also posted the same procedure for handling interrupts.
Type 0 interrupt requires hardware support. At the signal INTA
external device interrupt requests should be put on
data bus command code, which will be executed by the processor.
Typically, these teams are RST - command restart. It
These commands are called teams of software interrupts. Their
only 8: RST 0, RST 8, RST 10h, RST 18h, RST 20h, RST 28h,
RST 30h and RST 38h.Operand in assembler mnemonics - is not that
other than the branch address to the subroutine. Single-byte
commands RST in its action entirely analogous to the three-byte
commands CALL: RST 10h = CALL 0010h, etc. Having a data bus
code of any command RST, the processor it immediately perform
as well as the transition is made to the interrupt service
routine of type 0. RST command can be simply included in the
program, meaning they are not necessarily tied to the "real"
interrupt. Often the entry point to the most upotrebimye system
procedures are grouped under the entry point RST, than to make
substantial savings of memory by shortening Call of these
procedures. RST command does not affect the state enable /
disable interrupts. They are called software interrupt commands
in a purely formal, because they are still relevant to the
interruptions.
Command Code RST 38h - 0FFh, ie bytes of solid units.
Typically, such code is present on the data bus in a passive
state when no device is nothing on it does not expose (Data
bus, "tightened" to the chain of five in the resistor).
Actually This means that if you set the interrupt mode 0, the
transition is also will be performed at the address 0038h, as
in mode 1. Service interruption of type 0 takes more machine
cycles than type 1. In addition, the probability of failure on
the data bus is not equal to absolute zero.
By keeping it on interrupts, we simultaneously examined
another group of teams - RST.
0-th type of interruptions in the MSX (in exactly the same
in the "Spectrum") may be of interest only as an object of
knowledge. Its practical value is equal to its number.
In 0 second type interrupt the external device may expose
on the data bus code of any team, including the CALL or JP. If
you find that you want to take extra bytes teams
processor will generate the necessary number of cycles of
interrupt acknowledgment, in response to an external device to
be transferred missing bytes.
Interrupt a type 2 - the most powerful and most complicated.
Can specify up to 256 interrupt vectors, and each
(theoretically) put its manufacturing procedure. After
receiving an interrupt, the processor also independently send
the stack return address, and address the transition to serving
procedure formed as follows:
- Evaluates the full 16-bit vector as follows:
vector = 256 * I + SM, where I - value of the register I, and
SM - byte
data bus, put up her interrupt acknowledge cycle
tion (0FFh). In other words, the high byte of the address is
contained zhimomu register I, and the low byte is taken from
the data bus apparatus Conversely;
- To address calculation is read the word of the cells (e) and
(E +1). Received word and will address the transition.
Obtained is like double indirect addressing: first defined
mail addresses of the transition, and then he jump address.
Interrupt type 2 can get rid of the system serving the
procedures in circumstances where a BIOS-ROM is included in the
memory card. This situation occurs at work BASIC. If you write
a game type. GM,. OBJ, etc., to learn and type 2 Interrupts
have to. For. COM-programs much easier to change address in the
transition team at 0038h and leave type 1.
In the Spectrum interrupt type 2 are used in virtually
each toy, as in "Spectrum" get rid "of the system
ROM is impossible.
Command to set the interrupt mode has a mnemonic root
IM - Interruption Mode:
IM 0
IM 1
IM 2.
Download I register is possible only in a unique way:
LD I, A.
Reading the register I can provide valuable information: when
you run LD A, I trigger value interrupt enable flag is copied
to the P / V. In this way, a user program can learn whether to
allow interruption at the moment: P / V = 1 - enabled, 0 -
disabled.
In interrupt mode register 0 and 1 is not involved and I can
be used for program storage. When reading
LD A, I in addition to the flag P / V trigger zero flag Z and
the sign of S. In addition to downloading and reading through a
battery of other teams to register I do not.
Prohibition and permission to interrupt.
Disable interruptions to the performance of algorithms for
real-time, such as software or sound generation signal to write
the file on audiocassette, as well as switching memory card.
Often it is necessary to prohibit the interruption and at-risk
manipulations with the stack. Regime change interrupt also
better conduct proscribed by the interrupts.
Prohibition of interrupts:
DI (Disable Interruptions).
Interrupt Enable:
EI (Enable Interruptions).
An interesting feature: the interrupt is not resolved soon
EI, and at the end of the next command. So at the end of
interrupt service routine ...
EI
RET
new interrupt will never drive a wedge between EI and RET. So
automatically solve the problem of preventing the overflow of
the stack.
Non-maskable interrupt.
Non-maskable interrupts are initiated by applying low level
NMI input of the processor. The processor completes execution
of the current team, remembers a special flag to trigger
permission maskable interrupt prohibits masked interrupts sends
a return address stack and moves to address 0066h.Vyhod of
maintenance procedures carried out on the Interrupt nonmaskable
team RETN, which restores the state of maskable interrupt and
performs the normal RET.
Prohibit Non-maskable interrupts impossible.
Practical application nonmaskable interrupt vividly
illustrated in the "Spectrum" - with the help of the so-called
"magic button can be downloaded to disk all memory and then
to do with where the files anything you want. At the MSX input
signal NMI was put into the interface connector "common rail",
but built programmatic support to non-masked interrupt does not
have (done simply return). Therefore, the problem of extracting
the type of images of the games require individual programming.
Team return from interrupt masked - RETI.
For us, this team if it is of interest, the purely
lyubopytelsky. Full use of the RETI is possible only if the
priority interrupt controller, which he traces the emergence of
the RETI code and receiving the information so that one of the
devices, interrupt requests already served, allows other
devices to request interrupt their needs. Itself on its own the
RETI performs simply return type RET. To enable / disable
interrupts, it is not affected. For an ordinary return from a
maskable interrupt commands are used to EI and RET.
[To be continued].
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