Echo #06 30 июня 2000

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Iron - direct memory access controller sound card DMA Ultrasound Card.

    Direct memory access controller



   Direct memory access controller
(DMA, DMA - Direct Memory Access) provides high-speed data 
exchange between the I / O devices and memory without CPU 
utilization that freeing the CPU to perform calculations in 
parallel with the exchange and independently of it. Most often 
the possibility of RAP used to work with disk drives, but 
implemented using DMA adapters drives magnetic tape and a 
number of other devices. Tangible benefit in using

PDP during an exchange with the devices, sending or receiving 
data are sufficiently large portions at high speed. 

   In the PC-like computers that function performs DMA 
controller chip 8237A firm INTEL (Soviet analogue KR1810VT37)

or its analogs 8237A-4 8237A-5, operating with a clock 
frequency of 4 MHz and 5, respectively (standard IC 8237A 
operates at a frequency of 3 MHz). Controller has 4 independent 
channels, each of which can serve one peripheral device.



    1. The principles of operation of the controller DMA


   In RAP differ 2 main loop: loop, waiting (Idle cycle) and 
active cycle (Active cycle). Each cycle is divided into a 
number of states holding on time, one clock cycle

(Tick). From the cycle of the controller can wait
be transferred to a state program (Program Condition) by 
feeding on RESET input signal high-level duration of not less 
than 300 ns and the following These signal a low level (level

0) at the conclusion CS (Chip Select). In the state
Programming the controller is located as long as the withdrawal 
of CS signal remain low. In the process of programming the 
controller are given by: 


   - Starting memory address for the exchange;

   - Decrement the number before
     ferred bytes;

   - The direction of exchange


   and sets the desired modes (allow or deny a cyclic change in 
priorities, avtoinitsializatsiyu, set the direction of change 
of address in the exchange, etc.). 

   Download 16-bit registers of the controller via the 8-bit
I / O ports. Before loading the first (primary) byte must be 
cleared (Cleared), the trigger-latch (flip-flop the first / 
last, First / Last flip-flop), which changes its state after 
the withdrawal of port of the first byte and thus provides

The following commands output
the same port to load the high byte of the corresponding 
register. 

   Preset channel can be
unmask (bit mask channel is set to 0 in this case), after which 
it can receive signals, "Request for PDP", generated by an 
external device served through this channel. Signal

"Request to DMA" can also be initiated by setting the 1 bit 
request danogo channel in the case of requests of the 
controller. After the appearance of a request signal controller

enters the active cycle in which data is flowing. Exchange can 
take place in one of four modes: 

   1) single-mode transmission (Signle
Transfer Mode). After each cycle, the transfer controller frees 
the CPU bus, but immediately begins to scan signals request and 
as soon discovers the active request signal initiates the next 
transmission cycle. 

   2) Mode of transmission block (Block
Transfer Mode). In this mode, a signal request is required only 
until issuance of the controller signal Confirmation

request for PDP "(DACK), after which the bus is not
released until the transmission of the block.

   3) The transfer mode on demand (Demand
Transfer Mode). This mode is
intermediate between the first two: the broadcast is 
continuously up until active request signal, whose state is 
checked after each cycle of transmission. Once the device can 
not continue transfer, request signal is reset to them

and the controller halts.
This mode is used to exchange the slow device, allowing for
their temporal characteristics to work with
DMA block transfer mode.

   4) Threaded Mode (Cascade Mode). Mode allows you to include 
in the DMA subsystem more than one controller in cases

when four channels of DMA enough. In
this mode, one of the channels leading controller is used for 
cascading controller of the second level. To work

in a cascade of signal HRQ ("Request for capture")
slave controller is input to DREG
("A request for a channel PDP) leader, and the signal DACK (" 
Confirmation Request ") leading to the input HDLA (" 
Confirmation capture ") slave.


   This scheme is analogous to connecting
connecting the lead (first) controller
to the microprocessor, with whom he exchanged signals HRQ and 
HDLA. 


             2. Types of gears


         2.1. Transfer Memory to memory

           (Memory-to-memory DMA).


   Used to transfer a data block
from one location to another memory. Source
address is in register zero
channel output - in the registers of the first channel. The 
number of cycles of exchange (the number of bytes minus 1) is 
given in the register of the number of cycles channel 1. The 
transfer is done using the working register of the controller 
as an intermediary storage information. When peredache Memory 
to memory can be given a special mode of fixation address 
(Address hold), for which the value of the current address in 
register zero channel does not change, with the entire output 
memory block is filled with the same data element, located at a 
given address.



          2.2. Avtoinitsializatsiya

   (Startup, Autoinitialization).


   After completion of the transfer of conventional use of the 
channel PDP is masked and must be reprogrammed for further work 
with him. When avtoinitsializatsii masking the channel when the 
transfer is not occurs and the current address register and

cycle counter is automatically loaded
from the relevant registers with initial
values. Thus, to continue
(Repeat) The exchange is sufficient to expose
DMA request signal to the channel.


   2.3. Regime of fixed priorities.


   In this mode, channel 0 always has the highest priority and 
channel 3 - the minimum. This means that any transfer of 
channel with higher priority will be performed before the 
channel with more low priority.



   2.4. Cyclic shift of priorities.


   Allows you to avoid "hammering" tires one channel while 
simultaneously peredache on several channels. Each channel, on 
which the transfer is automatically assigned the lowest 
priority, then entitled to receive the transfer channel with 
the highest priority for which the transfer of currently 
possible. Thus, if at the beginning of the distribution of 
priorities was the usual (channel 0 - highest), and came to the 
DMA request signals on the 1 st and 2-th channel, it will first 
be carried out transmission on the first channel, then it will 
receive the lowest priority (and channel 2, respectively, the 
highest since a cyclic shift of priorities) and the transfer is 
executed by 2-th channel, which then gets lower

priority and highest priority will receive,
suitability, Channel 3, which will be
has priority for transmission.


       2.5. Compressing the time of transmission

       (Compressed transfer timing).


   If the timing characteristics
Performance exchanging devices
match, the DMA can reduce the execution time of each measure to 
transfer 2-cycle clock cycles due to waiting

included in each transmission cycle.


   3. Description of internal registers of the FPU.


   The controller has a 344-bit internal
memory, organized in the form of registers.
Description of internal registers of the FPU is shown in the 
table. 



          Name Bit Number

            register (bit) registers

 Register start address on April 16
 (Base Address Register)
 Register initial cycle counter 16 April
 (Base Word Count Register)
 Current address register April 16
 (Current Address Register)
 Register current cycle counter 16 April
 (Current Word Count Register)
 Working register address on Jan. 16
 (Temporary Address Register)
 Operating cycle counter register on January 16
 (Temporary Word Count Register)
 Status register 1 August
 (Status Register)
 Instruction register 1 August
 (Command Register)
 Mode register (Mode Register) on April 6
 Working register August 1
 (Temporary Register)
 Register masks (Mask Register) on April 1
 Register requests April 1
 (Request Register)



      3.1. Register start address

         (Base Address Register).


   In this case specify the starting address of RAM, which to 
begin the transfer. Register contains 16 bits and determines

address within the given memory bank size of 64K. Quest number 
of memory banks through special registers banks (Bank 
Registers), supported by external logic. Each channel has a DMA

its register and start address register
Bank. Such a division of memory banks
allows for sharing and memory unit, located at the intersection 
of the two banks. Each bank consists of four pages and begins 
with a page number, multiple of 4 (0, 1, 2, 3, 8, 9, 10, 11, 
and so etc.).



         3.2. Register entry

             loop counter

       (Base Word Count Register).


   In this case given the initial number of cycles to transfer 
a programmable channel. The actual number of transmitted

while the DMA data elements per unit exceeds a predetermined 
number of cycles, ie , if you ask 100 cycles of transmission, 
and element size is 1 byte, then for

session sharing will be transmitted 101 bytes of information.


       3.3. Current address register

        (Current Address Register).


   The initial value is entered in the register together with a 
register entry address. Later in the course of the transfer 
value of the current address is automatically increased or 
decreased (the actual direction of change is given when 
programming the register mode). If allowed 
avtoinitsializatsiya, then after the transfer to the register 
is automatically set to the register start address. 


  3.4. Register current cycle counter

      (Current Word Count Register).


   The register contains the current count of cycles (the 
number of remaining cycles of transmission). It appears in the 
number of cycles always one less than the number has not yet 
submitted data elements, so as to change the value in this 
register is late in the cycle of transmission, even after the 
actual transfer of data element, and the end of the transfer is 
recorded at the time of the overflow counter (the change of its 
value from 0 to 0FFFFh).



           3.5. Mode register

             (Mode Register).


   This register sets the operation modes
his channel controller.

 7 6 5 4 3 2 1 0

x x

                   The layout of bits:


                 0-1: Opening hours:

                    00 = write (in memory)

                    10 = read (from memory)

                    11 = invalid combination

                 2: Avtoinitsializatsiya:

                    0 = disabled

                    1 = allowed

                 3: Modify the current address in the exchange:

                    0 = increase

                    1 = reduction

                 4-5: Type of transmission:

                    00 = transfer mode on demand

                    01 = single transfer mode

                    10 = block transfer mode

                    11 = cascade mode


   Each of the four DMA channels has
its own set of registers, as described above. In addition, 
there is the following set of registers that are common to all 
channels. 


           3.7. Instruction register

           (Command Register).


   This 8-bit register controls the operation of
controller. It is programmed when
controller is in programming and cleared reset command
"Reset" and "Master Clear". Appointment of bits
command register is shown in the figure.

 7 6 5 4 3 2 1 0



                   The layout of bits:


                 0:0 = prohibit the transfer of the 
memory-memory 

                    1 = enable

                 1:0 = disable commit addresses in the channel 0

                    1 = enable

                 2:0 = unlock controller

                    1 = block

                 3:0 = normal timing diagram

                    1 = compression of transmission time

                      If bit 0 is set, then ignored

                 4:0 = mode fixed priorities

                    1 = reim cyclic shift of priorities

                 5:1 = mode extended recording

                    0 = delay in the recording

                      If bit 3 is set, then ignored

                 6:0 = active high signal level query

                    1 = Low DREQ

                 7:0 = active high signal

                    DMA request acknowledge (DACK)

                    1 = low



           3.8. Status register

             (Status Register).


   Register reflects the current status of requests and 
transmission on all four channels. Bits 0 - 3 are installed in 
the unit after completion of the transfer on channels 0-3 (bit 0

- Channel 0, bit 1 - channel 1, etc.), if
not specified mode avtoinitsializatsii. These bits
cleared after a reset command controller
and after each operation, read the state of the status 
register. 7.4 bits indicate which of the channels 0-3 is active 
in current demand signal to the FPU.



           3.9. Register masks

            (Mask Register).


   Every bit of this 4-bit register
masks / unmasks its channel DMA, and
The value of a mask channel, a value
0 unmasks the channel and allows the reception request signal 
from this channel. 


           3.10. Register query

             (Request Register).


   DMA request signal (DREQ) can be
published as a serviced unit, and
software. For the software publishing request signal on one of 
the 4-channel DMA you must install the appropriate bit

in a 4-bit register requests. Request
RAP can be canceled recording zero
values ​​in the corresponding bit in the register.
Bit is cleared automatically when a query
After transmission over the channel. All
request bits are cleared when you reset the controller. In 
order to perceive programmatic queries to the DMA channel 
should be be in the mode of block transfer.



          3.11. Work register

          (Temporary Register).


   This 8-bit register is used
to store the data item transmitted in the mode of a fixed 
address in the transmission memory, the memory or for temporary 
storage of bytes transferred for all other modes of 
transmission. 


         4. Software control

              DMA controller


   Software control of DMA controller
through I / O ports.
Access to each register of the controller can be implemented 
through its I / O ports. 

   The following table describes the ports
I / O controller used to control the FPU. The table shows
Only the high byte address, low byte
addresses for all ports the same. He
is # 77.


Port Mode Assignment

# 0C Record the initial address in the register entry

            address and current address register channel 0
# 2C record the same channel 1
# 4C recording the same for channel 2
# 6C record the same for channel 3

# 0C reading Reading the current address of the register of the 
current 

            Address Channel 0
# 2C reading, too, for channel 1
# 4C reading too, for channel 2
# 6C reading too, for channel 3

# 1C Record in the register entry loop counter and

            Register current cycle counter channel 0
# 3C recording the same channel 1
# 5C record the same for channel 2
# 7C record the same for channel 3

# 1C reading Reading the current value of the register of the 
current 

            cycle counter channel 0
# 3C reading the same for channel 1
# 5C reading the same for channel 2
# 7C reading the same for channel 3

# 8C Record DMA command register
# 8C reading Reading status register RAP
# 9C Record in the register requests RAP
# AC Record-bit mask for a channel DMA
# BC Record mode register for one of the channels of DMA
# CC Record Cleaning (reset) the trigger-latch (flip-flop of 
the first / 

            last)
# DC recording software reset of the controller
# EC record cleaning bit masks for all 4 channels
# FC Record register masks for all 4 channels
# DC
Reading or Reading working register RAP
# FC

# 07 Record Set bank number for channel 0
# 17 record the same channel 1
# 27 entry is the same for channel 2
# 37 entry is the same for channel 3



   Ports # 0C-# 7C are used for recording
original values ​​in the registers of primary and
current address, initial and current
loop counter for all 4 channels. So
as the eight-port, and registers in
through which they entered data
16-bit, the recording is done in two
admission. Prior to the first team O
the requested port to reset the trigger-latch, which holds the 
team output an arbitrary value to the port # CC,

after which the desired output port
byte of the 16-bit values ​​and then the high byte of the 
command output in the same port.


   Output to port # 8C allows you to place a value in the DMA 
command register (bits description command register is given in 
Section 3). 

   Reading from a port register reads # 8C
state of the FPU (Description of register bits
states are given in Section 3).

   Entry to the port # 9C allows you to set
or reset the request bit in the register of requests for a 
single channel. Instruction format following:


 7 6 5 4 3 2 1 0

The layout of bits xxxxx


                  0-1: Channel Selection 00-0

                                    01-1

                                    10-2

                                    11-3

                  2: 1 = set bit request for PDP

                      0 = reset bit request for PDP


   Entry to the port # AC allows you to set
or reset the mask bit in the register masks
for one channel. Command format:

 7 6 5 4 3 2 1 0

The layout of bits xxxxx


                  0-1: Channel Selection 00-0

                                    01-1

                                    10-2

                                    11-3

                  2: 1 = set bit mask

                      0 = reset the mask bit


   Entry to the port # BC sets the value in the mode register 
of one of the 4-channel DMA. Bits 0 and 1 specify the channel 
number (00-0, 01.01, 10-2, 11-3). In the recorded value of 7.2 
bits, respectively, transmitted in bits 0-6 mode register. 
(Description of register bits mode given in subsection 3).


   Entry to the port # DC sets the programmatic
Reset Controller (Master Clear). Output
any byte in the port has one and totzhe effect as a hardware 
reset of the controller. A soft reset command registers are 
cleared, conditions, requirements and working register. Also 
reset triggerzaschelka and installed all the bits in the masks 
register masks. After a soft reset controller goes into a cycle 
expectations. 

   Conclusion of any byte in the port # EC clears
register masks-resets bits of all four
DMA channels and thus allows
receiving requests for DMA on all channels.

   # FC port, you can specify an arbitrary value of the 
register masks the FPU. For this must be in bits 0-3 Register A 
establish the required value of masks channels 0-3 
respectively, and display this value in port.


   FPU registers banks are designed to
job number of the memory bank, which will be exchanged. Under 
the bank number refers to high-order bit number of the page

starting from 2-th bit. Recall that the architecture allows the 
PDP to work only with banks, memory size of 64K, and logic,

providing the bank switching is arranged so that the banks have 
stringent border described above. Because of this feature is 
not possible with RAP to exchange with memory blocks, crossing 
the border between two such banks. Each channel

PDP has its own register bank, so access to the channel memory 
is independent of any of the banks other channels, or from the 
ports of paging Memory (# 7FFD, # DFFD, # 1FFD, etc.).