[1/4] CP/M for Spectrum-128

Thu 12:46 23 Oct 1997 Nickolay Zabrodotsky writes to Pavel Fedin:

NZ> Is it possible to install CP/M on the Pentagon (i.e. on
NZ> a computer that does not contain it in ROM)?

The circuit will have to be modified.

Next I’m just throwing out my 1993 development - CP/M for Spectrum-128. In this
message there is a diagram, then a description.

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Scheme for finalizing the Spectrum-128 for using CP/M

A14+A15 NEW A14+A15
──────────────────── ──────────────────────────────┐ ........ ┌────────────
_________ │ ┌────┐ │
RESET CPU ┌───────┐ └──┤ 1 │ │
────────────────────┤R│ │ │ │ ├──┘
D4 ├─┤ │Q├────────┤ │
│ │ │ └────┘
│ │ │ │ LL1
A1 ┌────┐ ┌────────┤C│ │_│
─────┤ 1 │ │ ├─┤ │Qo────┐
A13 │ o────┐ │ +5 ──┤S│ │ │ │
─────┤ │ │ ┌────┐ │ └───────┘ │
└────┘ └───┤ & │ │ TM2 │
____ LE1 │ ├──┘ │
IORQ ┌────┐ ┌───┤ ││
─────┤ 1 │ │ └────┘ │
/WR │ o────┘ LI1 │
─────┤ │ │
└────┘ │ LI1
LE1 │ ┌────┐
└──┤ & │
│ ├──┐
_____ ┌──┤ │ │ _____
TRDOS │ └────┘ │ NEW TRDOS
──────────────────────── ────────────────────────┘ ........ └────────────

Now a few words. In order to install
CP/M on the Spectrum, you need to do the following: first, disable the ROM from the
processor address space, i.e. make sure that the
lower addresses have RAM, and secondly, make the
1818VG93 ports available. Using the above circuit, the 0DFFDh
port with one control bit D4 is implemented. Why the fourth bit and not the zero bit? The fact is that port 0DFFDh is a standard memory management port
(CMR1) for Sinclair PROFI. And its fourth bit controls the presence/absence of ROM in the address space of the processor. Therefore, on a regular 128 Spectrum
one bit of CMR1 is actually implemented (it follows thatfor
PROFI there is no need to do any modifications :)))

Let's see how the ROM is turned off. You need to find an element in the Spectrum circuit on which the addresses A14 and A15 are logically added up. The output of this element (signal A14+A15) determines where the data will be sampled from. Those. when A14==0 and A15==0
(address range 0000-3FFFh), then fetching from ROM takes place, and when
or A14==1, or A15==1 (address range 4000h-0FFFFh) - fetching from RAM.
What needs to be done? You need to break the signal A14+A15 and insert an OR element into the gap, logically adding A14+A15 with the
value written to port 0DFFDh. If the port contains 0, then the same A14+A15 is removed from the OR element (LL1) and no changes occur in the ROM/RAM selection. But if the port contains 1, then the new signal A14+A15 will always be equal to one, and, regardless of the address, the sampling circuit will always access RAM. As a result, in addresses 0000-3FFFh there will be a zero RAM page.

Now as for the 1818VG93. During normal operation, BETA disk ports 1Fh, 3Fh, 5Fh, 7Fh, 0FFh (0BFh) are inaccessible so as not to conflict with other devices (1Fh - Kempstone port,
1Fh, 3Fh, 5Fh, 7Fh - 580BB55, 7Bh - printer (conflict due to
incomplete decryption)). When TR-DOS is accessed,
together with ROM switchingaccess to the ports of the
controller is allowed. In the diagram you need to do the following: look for element LA2 on the circuit
BETA disk - this is an eight-input AND-HE element.
The output of this element through the OR element (and possibly a diode)
goes to the Reset signal of trigger TM2. I named the direct output of this trigger /TR-DOS. When TR-DOS is not working and the ports
are unavailable, it is equal to 1, and when TR-DOS is running and the ports are available, this signal is equal to 0. It is this signal that needs to be broken
and a logical AND with the inverse output
of the assembled port 0DFFDh placed in the gap. When port 0DFFDh contains 0, its inverse output is 1 and the new /TR-DOS signal is no different from the old one. And if 1 is written to the port, the inverse
output is equal to 0 and the new signal /TR-DOS is always equal to 0, i.e.
the disk drive controller ports are available.

That, in fact, is all that concerns the circuit. Write the value XXX0XXXXb to port
0DFFDh - normal spectrum. We write
XXX1XXXXb - the ROM is turned off and the ports
of the controller become available. Yes, and one more thing - you can set a switch that prohibits the operation of port 0DFFDh. You can either simply open the signal going to the trigger's C input, or short-circuit the R
trigger's input to ground (see.схему).

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Best wishes! Michael KLUG