Methods for achieving technological independence in computing systems

06 November 2025

DMITRY MIKHAILOVICH BYSTROV, Lead Software Engineer
Ryazan Design Bureau "Globus," Ryazan, Russia

METHODS FOR ACHIEVING TECHNOLOGICAL INDEPENDENCE IN THE FIELD OF COMPUTING SYSTEMS

This paper proposes methods for Russia to achieve technological independence in the production of computers (computing systems). It examines the challenges associated with the use of foreign components and outlines the technologies and existing developments currently available within Russia. It also describes potential student projects designed to foster the growth of a domestic tradition in computer engineering (such as developing a processor, a video controller, or a home-based laboratory for chip fabrication).

Keywords: computing system, computer, processor, video controller, lithography, economy, security, bloat.

Introduction

A typical desktop computer from the late 1990s featured 8-16 megabytes of RAM, operated at a clock speed of 100-300 MHz, and consumed approximately 150 watts - half of which was accounted for by the monitor. The standard operating system of that era, Windows 98, officially required 16 megabytes of RAM to run. This was considered somewhat extravagant compared to Windows 95, which required only 4 megabytes of RAM (including a web browser) - a configuration even sufficient for the layout of glossy magazines using PageMaker 5.0. Back then, there were still many users of legacy machines who managed to accomplish all their tasks - ranging from mathematical and accounting calculations, document and graphic editing, FidoNet correspondence, and BBS chatting to software compilation, PCB layout, writing term papers and theses, and playing various computer games - with just 128 KB to 1 MB of RAM.

A modern desktop computer typically features 8 GB or more of RAM, operates at 3 GHz or higher (with 4 or more cores), and consumes 300 watts of power. The modern Ubuntu 26 operating system officially requires at least 6 GB of RAM and a dual-core processor running at 2 GHz [1]. Yet, the actual functionality available to the user has barely expanded. Furthermore, the size of individual software applications (such as Microsoft Word, Adobe Photoshop, Adobe Reader, ACDSee, Opera, Nero, Skype, and their equivalents) and software environments (Java, .NET, DirectX, OpenGL - excluding video memory) has increased by two to three orders of magnitude.

Hard drive space requirements have similarly grown by two to three orders of magnitude: Windows 95 required 50 MB, Windows 98 needed 200 MB, while Ubuntu 26 demands 25 GB. (It is worth noting that the core technologies for hard drives - including SSDs - are currently held only by the United States, Japan, South Korea, and China; the corresponding manufacturing facilities in Europe were shut down during the 2000s.)

Let us examine some of the technologies that have driven up system requirements - a phenomenon known as "software bloat":

Modern operating systems run hundreds of drivers and services simultaneously, most of which serve no meaningful purpose for the user.
Compilers have increased the size of the generated code. An entirely empty program compiled with GCC now takes up 15 kilobytes (tens of kilobytes on Windows) and requires external libraries (static linking can push this to around a megabyte). For comparison, an empty program in Turbo C weighed less than a kilobyte and required no external libraries, while assembly-language programs were even more compact (For example, a minimal Tetris for ZX Spectrum has a size of 189 bytes [Bystrov D.M. Tetris 189b / Info Guide #14 (Electronic resource) http://alonecoder.nedopc.com/zx/books/IG14.zip], 15 KB is a size of a whole disk manager, text editor or a compiler [Системный SOFT для настоящих синклеристов / Virtual TR-DOS (Electronic resource) http://vtrd.in/system.htm].). These tens of kilobytes of overhead for every single task create a cumulative effect, compounding the issues mentioned in the previous point.
External libraries often contain code that goes unused by the specific program. However, due to library version incompatibilities, the necessary library files are typically bundled alongside the program. For instance, with Qt5, the external libraries required for a console application weigh in at 8 megabytes; for a graphical application, that figure rises to 20 megabytes, and with network support, it exceeds 100 megabytes.
Device drivers have grown significantly in size - partly due to the factors mentioned above, but also because modern protocols have become unnecessarily complex. Even a simple mouse driver can now take up megabytes of space.
Software installers (whereas in the 1990s, programs could usually be run without an installer) often require the hard drive to store not only the installed software itself but also the original distribution package, along with a copy on the system partition. In many cases - such as with Microsoft Office, web browsers, iTunes, or Windows updates - these copies are never deleted, not even when a newer version is installed. Consequently, the system disk gradually fills up, eventually forcing the user to purchase a new, higher-capacity drive. Google's Android operating system functions in much the same way.
Applications packaged in formats like Snap, Flatpak, or AppImage can consume up to five times more disk space than conventional programs. These containerized formats have now become the default standard for Ubuntu.
New data formats. For instance, the .doc format could be edited even on a machine with less RAM than the size of the document itself. In contrast, formats like .docx and .odt require unpacking an archive, reading the .xml files contained within, and then repacking everything upon saving. In the realm of graphics, resource-intensive formats such as JPEG2000 and WebP have emerged. As for video, the H.264 codec once forced users whose processors had a data cache smaller than 32

kilobytes to upgrade their hardware. Since then, codecs like H.265, H.266, VP8, VP9, and AV1 have appeared, which increased the overhead of decompression by two to three orders of magnitude. As a result, any YouTube user is now effectively forced to purchase processors that include hardware acceleration for these codecs (which entails the addition of tens of millions of transistors). The YouTube platform is controlled by Google (Alphabet).

Frameworks like Electron (used in many modern messaging apps) essentially bundle a full-fledged web browser. They consume hundreds of megabytes of RAM and significantly slow down rendering.
New standards for the Internet itself have rendered both older browsers - which, back in the 2000s, functioned perfectly well on just 16 MB of RAM - and older processors obsolete. This point deserves further elaboration.

Websites in the 2000s typically consisted of text and images, making them quite lightweight. Over time, however, a trend emerged toward increasingly complex scripts and the integration of entire JavaScript engines - to the point where sites simply ceased to function on older browser versions (even when this wasn't due to any actual increase in site functionality). Sites like Habr.ru and Lichess.org, for instance, followed this path. Meanwhile, newer browser versions gradually shifted toward the resource-intensive Chromium engine, which is also controlled by Google.

Encryption (Transport Layer Security, TLS) is a major consumer of computational resources. The standard for encryption is the AES-128 algorithm, with a gradual transition toward AES-256. Processing every 16 bytes requires approximately 1,000 mathematical operations (the same operations are deliberately repeated multiple times). Consequently, modern Intel and AMD processors include specialized instructions known as AES-NI, which accelerate this specific encryption algorithm by at least a factor of ten (as compared to non-AES [AES-NI SSL Performance / CALOMEL (Electronic resource) https://calomel.org/aesni_ssl_performance.html].). Google Chrome and its derivatives - which encompass virtually all modern browsers - label sites lacking TLS as "not secure," requiring additional user action to access them. Furthermore, the Google search engine penalizes sites that operate over standard HTTP by lowering their search rankings. Consequently, even websites that serve nothing more than plain text are effectively forced to transition to HTTPS. The HTTP/2 protocol, which has been a standard since 2015, cannot function without TLS; notably, Google employees were the primary architects of HTTP/2 (Mike Belshe and Roberto Peon [Belshe, M., Peon, R. Hypertext Transfer Protocol Version 2 (HTTP/2) / RFC Editor; https://doi.org/10.17487/rfc7540] [Belshe, M., Peon, R. SPDY Protocol - Draft 1 / Chromium (Electronic resource) https://www.chromium.org/spdy/spdy-protocol/spdy-protocol-draft1/].).

Beyond encryption itself, the "handshake" process required to establish a connection is highly resource-intensive. It involves a key exchange based on the Elliptic Curve Diffie-Hellman Ephemeral algorithm (a standard since 2018). Calculating the key requires roughly a million elementary mathematical operations, excluding various auxiliary tasks (The most efficient implementation, based on redisue number system, takes 110 000 clocks on an FPGA [Hung Nguyen, Trang Hoang, Linh Tran. Efficient Hardware Implementation of Elliptic-Curve DiffieHellman Ephemeral on Curve25519 / Electronics 2023, 12(21), 4480; https://doi.org/10.3390/electronics12214480].). On a Pentium 100 processor, this would take about 15 seconds, and on a Celeron 300, around two seconds; however, since modern websites typically establish multiple simultaneous connections, such a process would likely never complete on older hardware.

It is also worth noting that executives frequently move between Google, Intel, and AMD (among the top managers, for example: Jim Keller [btarunr. Ryzen Architect Jim Keller Joins Intel / www.techpowerup.com (Electronic resource) https://www.techpowerup.com/243673/ryzen-architect-jim-keller-joins-intel], Robert Hallock [kavagangga. Роберт Халлок присоединился к Intel / i2HARD (Electronic resource) https://i2hard.ru/publications/33315/], Uri Frank [Uri Frank / Google AI and Infrastructure (Electronic resource) https://techsysinfra.google/aboutus/tsi-leaders/uri-frank/], Dan McNamara [Dan McNamara / AMD (Electronic resource) https://www.amd.com/en/corporate/leadership/dan-mcnamara.html], Raja Koduri [Shilov, A. Legendary GPU architect Raja Koduri's new startup leverages RISC-V and targets CUDA workloads Oxmiq Labs supports running Python-based CUDA applications unmodified on non-Nvidia hardware / Tom's Hardware (Electronic resource) https://www.tomshardware.com/tech-industry/artificial-intelligence/legendary-gpu-architect-raja-koduris-new-startup-leverages-risc-v-and-targets-cuda-workloads-oxmiq-labs-supports-running-python-based-cuda-applications-unmodified-on-non-nvidia-hardware].), and all three companies share the same owners (Except for the Google founders, the main shareholders of Google (Alphabet), Intel and AMD are Vanguard and BlackRock funds [https://finance.yahoo.com/quote/GOOG/holders/] [https://finance.yahoo.com/quote/INTC/holders/] [https://finance.yahoo.com/quote/AMD/holders/], the same with Seagate [https://finance.yahoo.com/quote/847.F/holders/], Western Digital [https://finance.yahoo.com/quote/WDC.F/holders], Microsoft [https://finance.yahoo.com/quote/MSFT/holders/], Apple [https://finance.yahoo.com/quote/AAPL/holders/] and some other american companies.).

Many users view computers primarily as tools for playing video games. Yet, the technologies required to achieve photorealism and cinematic quality - to say nothing of actual gameplay - were already realized a decade ago. In recent years, the game development industry has been subject to the same trend of "software bloat." Even among older games, one can find visuals that hold up quite well by modern standards - for instance, Shadow of the Colossus, Gran Turismo 4, and Metal Gear Solid 3 on the PlayStation 2. That platform featured only 32 MB of RAM and 4 MB of VRAM, and it was manufactured using 250nm process technology - a standard that was, and remains, well within the reach of both Russia and the European Union.

The European Union (EU) spends approximately 80 billion euros annually on the purchase of foreign-made computing hardware (Counted from the sum using the provided coefficients [EU import/export stats in 2024 / ec.europa.eu (Electronic resource) https://ec.europa.eu/eurostat/web/products-eurostat-news/w/ddn-20241004-1].). This sum is comparable to the cost of building several microchip fabrication plants - even those capable of 28nm precision, which is sufficient for hardware like the PlayStation 4, to say nothing of computers intended for office, military, or specialized use. The EU already possesses 28nm-capable fabrication facilities in Germany and France, and it also produces advanced lithography equipment, optics, and lasers. Yet, despite this, the EU has not manufactured its own processors, memory, or hard drives since the 2000s. Consequently, the entire EU computing infrastructure - including the transmission of classified data - is tethered to the United States, providing a mechanism for political pressure on the European Union.

Russia spends roughly 10 billion dollars a year on foreign-made computing hardware and microchips (Sum of all categories [Статистика по импорту высокотехнологической продукции в РФ / tadviser.ru (Electronic resource) https://www.tadviser.ru/index.php/%D0%A1%D1%82%D0%B0%D1%82%D1%8C%D1%8F:%D0%AD%D0%BA%D1%81%D0%BF%D0%BE%D1%80%D1%82_%D0%B8_%D0%B8%D0%BC%D0%BF%D0%BE%D1%80%D1%82_%D1%8D%D0%BB%D0%B5%D0%BA%D1%82%D1%80%D0%BE%D0%BD%D0%B8%D0%BA%D0%B8_%D0%B2_%D0%A0%D0%BE%D1%81%D1%81%D0%B8%D0%B8#.D0.98.D0.BC.D0.BF.D0.BE.D1.80.D1.82_.D1.8D.D0.BB.D0.B5.D0.BA.D1.82.D1.80.D0.BE.D0.BD.D0.B8.D0.BA.D0.B8_.D0.B2_.D0.A0.D0.BE.D1.81.D1.81.D0.B8.D1.8E_.D1.81.D0.BE.D0.BA.D1.80.D0.B0.D1.82.D0.B8.D0.BB.D1.81.D1.8F_.D0.BD.D0.B0_1.2C5-2.25].). While this amounts to approximately 1 trillion rubles, the expenditure is in foreign currency - funds generated through the sale of Russian natural resources. For comparison, the annual budget of Roscosmos is one-third of that amount and is denominated in rubles (Less than a trillion rubles for 3 years [Статецкий, Е. Россия планирует потратить на космос почти триллион рублей в 2025-2027 годах / Прокосмос (Electronic resource) https://prokosmos.ru/2024/09/30/rossiya-planiruet-potratit-na-kosmos-pochti-trillion-rublei-v-2025-2027-godakh].).

Beyond hardware, there is also significant spending on foreign software and related services, such as subscriptions, cloud storage, in-game transactions, technical support, and consulting. This is partially offset by the sale of Russian-developed software to certain friendly nations. Within the EU, some countries (such as France) even run a surplus in software exports; however, this surplus does not cover the cost of purchasing the hardware on which that software runs.

Furthermore, there is the factor of commercial risk. A foreign architecture could suddenly change in such a way that domestic software written for it - or domestic hardware designed for it - will cease to function. For example:

the introduction of a new boot standard (potentially one that only supports "trusted" operating systems);
changes to peripheral protocols (this could even affect display output);
the disappearance of certain types of peripherals (such as COM, LPT, ISA, or PCI ports);
the emergence of hidden interrupts, which disrupt real-time software (a scenario that has actually occurred);
the end of support for older operating systems (and any independent OS will inevitably encounter the issues listed above).

Beyond financial considerations, there is also the issue of security. Foreign-made processors, chipsets, network switches, and even removable devices often contain their own internal operating systems that are impossible to monitor or control. Furthermore, foreign software may include "backdoors" - hidden mechanisms designed for surveillance, disruption, or the interception of operations via external commands - which can remain undetected for years, even when the source code is available (For example, such backdoors have been found in Linux [https://www.anti-malware.ru/news/2022-02-24-111332/38233] [https://habr.com/ru/company/ruvds/blog/677662/] [https://www.linux.org.ru/news/security/17333365] [https://m.habr.com/ru/post/484436/comments/#comment_21153658], in FreeBSD [https://aftershock.news/?q=comment/15726311#comment-15726311], in sudo [https://m.habr.com/ru/company/mailru/blog/515134/], in vim [https://www.opennet.ru/opennews/art.shtml?num=50857], in PolarSSL [(https://polarssl.org/tech-updates/security-advisories/polarssl-security-advisory-2014-04], in liblzma [https://www.openwall.com/lists/oss-security/2024/03/29/4], in node-ipc [https://www.opennet.ru/opennews/art.shtml?num=56870].). Moreover, "Ken Thompson hack" (a malicious insertion in a self-compiling compiler) might not even appear in the compiler's source code at all.

Billions of dollars in annual costs, commercial risks in software and hardware development, the loss of information security, and external political pressure - this is the price of technological dependence.

Defining the Objective

It is important to distinguish between technological independence and import substitution. Import substitution may address individual system components, but if there is no control over the key components, the entire technological chain collapses. Technological independence implies that the entire technological chain remains within the country (as was the case in the USSR, and as is currently observed in the PRC). It is this second scenario that concerns us here.

Achieving technological independence in the field of computing requires:

The production of processors.
The production of RAM. One cannot use an operating system that requires gigabytes of memory if the necessary memory capacity cannot be provided. Furthermore, the interfaces for desktop computer RAM change every six years; therefore, one cannot rely on imported memory for long-term projects.
Display production. Relying solely on foreign-made displays carries the risk that their connection ports may change - as we have seen happen repeatedly (e.g., TV, AV, SCART, CGA/EGA, VGA, DVI, HDMI, DisplayPort, Thunderbolt). Moreover, such displays might eventually support only "trusted" operating systems, to enforce "copyright" protections when displaying content.
Video controller production. This is closely linked to the previous point.
A fully independent software ecosystem (primarily requiring an operating system, a development environment with a compiler, an office suite, networking software, and a database management system). The drawbacks of using foreign software - including "open-source" software - have been discussed above. Independent software ecosystems have been established by companies and platforms such as Microsoft, Apple, IBM, Sony, Samsung, ZX Spectrum, and Amiga, among others. In other words, this is a standard practice - all the more so given the bloated nature of American "open-source" software and protocols.
Peripheral production (keyboards, mice, printers, scanners, etc.). Foreign manufacturers can discontinue any product at any time, particularly those using "outdated" interfaces - a practice known as planned obsolescence.
Production of hard drives and removable storage media. This existed in the USSR and the COMECON countries, though it lagged behind imported alternatives and was eventually discontinued.
Production of the manufacturing equipment required for all the items listed above.
Production of the consumables needed for the manufacturing of all the items listed above.
Production of the metrological equipment and standards required for all the items listed above.

Proposed Solutions

It should be noted that technologies such as the 28 nm node are considered strategic and are not sold to private entities or to countries like Russia and the PRC. Consequently, any efforts toward achieving technological independence in Russia must be based on technologies that have already been mastered: the 350 nm node (for which domestic equipment is produced) and, potentially, the 90 nm node (for which Russia possesses foreign-made equipment). Once fully mastered, the 90 nm technology can be utilized indefinitely; it is relatively cost-effective - not requiring, for instance, double-patterning - and its capabilities are sufficient for producing gigabit-scale DRAM chips or processors containing over 100 million transistors at clock speeds of at least 3 GHz, such as the dual-core AMD Opteron or the 8-core Cell processor (used in the PlayStation 3). Naturally, achieving such clock speeds requires designing processors at the level of physical topology, rather than by assembling pre-existing functional blocks.

Key centers of expertise include the PJSC "Element" group - which encompasses NIIME/Mikron (Zelenograd), NIIET/VZPP (Voronezh), Svetlana-Semiconductors (St. Petersburg), and others [2] - as well as the Zelenograd Nanotechnology Center, which develops steppers and microchips and provides packaging services, including 3D assembly [3]. Additional expertise can be found at firms such as MCST and Milandr, as well as at institutions including MEPhI, the Lebedev Physical Institute (FIAN), and the Scientific Research Institute for System Development of the Russian Academy of Sciences (NIISI RAS), the latter of which operates a pilot production facility based on the 250 nm node [4]. "Element" also organizes advanced training and internships for students and professionals, and offers contract design and manufacturing services, including the 90 nm technology (Teaching and staging: [Карьера / Группа компаний Элемент (Electronic resource) https://gkelement.ru/career/], contracted fabrication: [Производственные и инжиниринговые услуги и работы / Mikron (Electronic resource) https://mikron.ru/services/], contracted fabrication down to 90 nm [Контрактное производство / Mikron (Electronic resource) https://mikron.ru/services/kontraktnoe-proizvodstvo/].).

There have been reports that Russia possesses units of the Japanese "Minimal Fab" system - equipment capable of producing individual microchips at a low cost (With 6 um precision [amartology, checkpoint. Комментарии / Российская микроэлектроника два года спустя / Хабр (Electronic resource) https://habr.com/ru/articles/801931/#comment_26645385 https://habr.com/ru/articles/801931/#comment_26648943].) - though their exact location remains unknown.

Separately, there is an international "Hacker Fab" movement, which has documented a DIY lithography setup built using a standard microscope and other off-the-shelf components. In Russia, one such setup exists at the Lebedev Physical Institute (FIAN) [5]. It offers a manufacturing precision of up to 1.5 um [6]. However, all known users of these setups operate without a cleanroom or even a basic glovebox; they adjust focus by eye and have yet to determine the optimal parameters for photoresist thickness, exposure time, and development time. The optics themselves are capable of 1 m resolution [7].

For students, FPGA-based development is a readily accessible option. Evaluation kits start at 835 rubles (Chinese chips Gowin [Демонстрационные платы SIPEED TECHNOLOGY LIMITED TANG NANO 1K / Гамма плюс (Electronic resource) https://vyborg.icgamma.com/catalog/demonstratsionnye-platy/tang-nano-1k-sipeed-technology-limited-skl/].), with offerings available from manufacturers such as Altera and Xilinx, as well as domestic firms like VZPP [8] and Milandr [9]. If necessary, a design written in Verilog can be ported to an ASIC by any of the aforementioned technology centers. It is also possible to manufacture chips using domestic gate arrays (base matrix chips), including those that incorporate analog components. Students should collaborate to pursue complex, engaging projects - for instance, through initiatives like NedoPC [10] or Tiny Tapeout [11]. The NedoPC movement, which is primarily Russian-based, has - through the efforts of just a few individuals - produced several models of home-built computers, along with custom operating systems and a wide range of software [12].

Let us examine the implementation options for each of the system's components.

Processor manufacturing: In 2014, the Mikron plant (Zelenograd) produced a batch of the Elbrus-2SM - a dual-core processor operating at 300 MHz (90 nm) and developed by the company MCST [13]. The Research Institute for System Development of the Russian Academy of Sciences (NIISI RAS) developed and manufactured KOMDIV processors with clock speeds of up to 66 MHz [4]. Other domestic designs that can be manufactured in Russia also exist, notably the "Multiclet" [14] and microcontrollers from the company Milandr [15].

Thus, Russia is certainly capable of producing processors, even if they do not yet compete with imported counterparts. However, by fostering a technological tradition and ensuring demand for new designs, it is possible to develop processors capable of powering high-end workstations. Specifically, one could focus on relatively small, massively parallel cores - utilizing inter-core ports that bypass shared memory (similar to the architecture of transputers).

A typical core might contain 16 arithmetic registers, 2-4 FMA (fused multiply-add) units - which can be used to construct other arithmetic operations, including division via the Goldschmidt algorithm, - 32-64 kilobytes of addressable high-speed memory ("scratchpad"), and a switching circuit for logical operations and bit shifts. The cores control unit should include dedicated registers for addresses, the stack, and counters, as well as a prefetch buffer capable of holding 32-64 operations, with the ability to execute up to 16 of these simultaneously (encompassing memory and address-register operations, as well as logical and shift operations that do not involve the FMA units). The selection of operations to be executed should be determined by tracking data dependencies (analogous to the "Multiclet" processor) and by renaming dependencies during function calls and returns (similar to the SPARC processor). It is also advisable to implement automatic renaming of address registers when invoking methods of another class and returning from such calls. Other optimizations for object-oriented programming (OOP) operations could be included - such as object alignment, prefetching objects based on an address stored in their first word, and caching virtual method tables - along with accelerations for other frequent operations, including typical OS tasks like context switching and inter-process data transfer via hardware-implemented pipes. It is important to incorporate hardware-based short-loop constructs (e.g., REP, REP2, REP3, etc.) that specify the number of subsequent instructions; this avoids the use of conditional branch instructions within short loops and prevents pipeline flushes. Automatic renaming for loop variables (Ai = Ai-1) could also be implemented. Furthermore, a hardware-level ternary operation for short-branch logic is desirable.

The internal representation of instructions could take the form of an "extended" RISC architecture, where the operation and the types of its parameters - such as input data, call arguments, loop variables, global/local variables (with or without destruction upon access), internal/external memory, I/O ports, or special-purpose registers - are defined separately from the specific tags assigned to data of a given type (with 4-8 tags available for each type). For the external representation, this first component can be compressed into 8 bits using a compact lookup table, which could even be loaded on a per-process basis. Consequently, three-address instructions can be encoded in a 2-byte format, with only the numeric or address-based parameters requiring additional bytes. Constants wider than 8 bits will be rare, since hardware support for OOP allows methods to be invoked by their index. It is also worth noting that some instructions can be 8 bits long and require no parameters (including operations involving previous and pre-previous results). This allows for fetching more instructions per clock cycle - for instance, via a 64-bit bus.

In any case, there is a vast design space for increasing the number of instructions per cycle and enhancing the efficiency of individual instructions - including approaches never before seen in foreign-designed processors. Simply copying existing designs is a dead end.

The proposed design is fundamentally incompatible with MIPS, ARM, SPARC, POWER, and RISC-V architectures - even as an extension - at least because these architectures lack a distinction between arithmetic and address registers. While x86/amd64 architectures do technically feature address registers and ports, their instruction sets cannot represent three-way data dependencies. This, for example, precludes the early execution of function calls and returns - operations that would otherwise need to wait for the completion of arithmetic

calculations. Furthermore, these architectures typically conflate the call stack and the data stack, which wastes clock cycles during calls and returns. While x86 offers some support for short loops, it is limited to loops consisting of a single instruction. Moreover, none of these architectures distinguish between internal and external memory, preventing the effective use of scratchpad memory.

A custom architecture could also accelerate the fundamental multiply-accumulate (FMA) operation - for example, by storing numbers alongside their bit-level carries. Instead of storing a carry for every single bit, one could store carries every 4 or 8 bits; the final assembly of these values into a standard format could then be performed directly on the data paths as the numbers are transferred from the FMA units to memory or other destinations. Depending on the bit-width and the number of FMA (fused multiply-add) units, the described architecture would require between 100,000 and 400,000 transistors per core - covering the "hot zone," control logic, external interface controllers, and buffers - plus another 2 to 4 million transistors for scratchpad memory. For comparison, modern high-performance cores - which feature 256 general-purpose physical registers, vector units, speculative execution, and hardware accelerators for specific protocols - contain around 300 million transistors (excluding caches), while so-called "energy-efficient" cores contain about 20 million. Consequently, we can easily achieve superior performance per transistor. This allows such processors to be manufactured using less advanced, "coarser" process nodes - ranging from 1-micron technology (feasible even in a home-lab setting, using external SRAM for scratchpad memory) to more sophisticated nodes. Using 90nm technology - which is currently available in Russia - it is possible to integrate over 100 cores, each running at 3 GHz, onto a single die. With 100 cores, each equipped with local memory and inter-core interconnects, one can efficiently pipeline workloads such as video and audio processing, database management, server operations, and CAD (computer-aided design). Even at the 90nm node, such an architecture can deliver speeds that outperform existing processors for these types of tasks.

Developing an optimal computer architecture is a significant and compelling challenge. Its scientific value has often been overshadowed by commercial priorities - such as maintaining binary compatibility, inflating performance-per-clock metrics through vector operations, and tailoring specific processors to handle particular protocols (e.g., RSA, VP9).

Binary compatibility is irrelevant when developing software in high-level programming languages; only the system configuration truly matters. There are indications that large language models based on neural networks - including free ones like Qwen - are already capable of porting software to specific environments. Given the necessary political will, it would be possible not only to recompile existing software but even to rebuild an entire suite of application software from scratch. For context, in 1994, Microsoft had a total workforce of 15,257 people (Accounting data, including all the staff and possibly people that went away that year [The History of Microsoft - 1994 / Microsoft (Electronic resource) https://learn.microsoft.com/en-us/shows/history/history-of-microsoft-1994].), yet they were simultaneously developing Windows 95, Windows NT, Windows CE, an office suite, a database management system, a visual development environment with a C++ compiler, a web browser, electronic reference systems, and several games of varying scale. Today, companies and groups such as Sber, VK, Yandex, the "1C:Franchising" network, and AFK Sistema (which includes MTS, Ozon, and others) - each individually - surpass the scale of the 1994-era Microsoft. Furthermore, there are several other Russian firms that each employ thousands of programmers (e.g., Kaspersky, X5, T-Bank, Alfa-Bank, Wildberries, etc.).

Simple processor cores can easily be written in Verilog by a single student, often requiring fewer than a thousand lines of code. Additionally, open-source cores are readily available on platforms like OpenCores and GitHub.

RAM production. The largest Russian-made RAM chip has a capacity of just 2 megabytes (SRAM); however, a 72-megabit SRAM chip (with a 36-bit bus) has also been designed, though it has yet to be tested at domestic manufacturing facilities. While DRAM chips are not currently produced in Russia, the underlying technology is not a secret (this includes DDR2, which is used in conjunction with the Elbrus-2SM processor). Existing 90nm process technology is sufficient for producing gigabit-capacity DDR2 chips, which can be assembled into standard 1-2 GB memory modules - more than enough for a typical office PC. Consequently, it is entirely feasible for Russia to achieve independent production of RAM. Over time, it will be necessary to expand production using the 90 nm process, as RAM is a high-volume product. Existing stockpiles of DDR2 will not be sufficient for the millions of new computers being built.

Having in-house RAM production is also important for manufacturing specialized types of RAM - for instance, memory optimized for the operation of neural networks (hardware-based convolution operations) and/or optimizations for object-oriented programming (lists, queues, hardware-accelerated heap management).
Display manufacturing. The technology involved here is not as highly refined as that used for processors and memory. The USSR produced cathode-ray tube (CRT), liquid-crystal (LCD), and plasma displays; however, the technology for plasma displays was exported/lost in the 1990s, while the production of CRT and LCD units was phased out in the 2000s. Currently, Russia only produces miniature OLED displays [16]. While it is possible to assemble larger panels from smaller OLED units, the seams between them remain visible. A better approach would be to manufacture full-scale display matrices with an LVDS interface, following the accessible models established by Chinese manufacturers. This challenge has yet to be fully addressed, though the "Reflektor" plant in Saratov - which once produced LCDs - now manufactures LED-based advertising panels [17].
Video controller manufacturing. Proprietary video controllers were developed for the "Elbrus" and "Baget" systems. Designing video controllers is a classic exercise in learning FPGA-based development. It is worth noting that, over the past few decades, DRAM speeds have not increased as dramatically as processor speeds. Today, the cycle time for high-end graphics DRAM is approximately 45 ns, compared to 260 ns for the classic Soviet 565RU7 chips, and roughly 130 ns for the 565RU15 (Produced in 1992; the shown digits indicate the access time of 60 ns [565ая серия / 155la3.ru (Electronic resource) http://www.155la3.ru/k565.htm]).) or similar chips, such as the 44256 (1Mbit/4) series. These legacy chips, manufactured using 1.2-micron technology (comparable to what might be found in a modern home lab), were capable of sequential reads every 60-70 ns - roughly the time required for one television pixel, or two pixels at resolutions up to 800x600. Additional clock cycles are consumed during line transitions (every 512 bytes) and row refresh operations (accounting for approximately 1% of total time). By operating these chips in parallel, they can still be utilized today to construct video controllers.

As an example, let us consider a 3D-capable video system, similar to the PlayStation 2 (with some relative strengths and weaknesses). Unlike the PlayStation 2, we will separate the video memory from the texture memory. At a resolution of 640x400 (interlaced television signal), the pixel clock frequency would be approximately 14 MHz (70 ns per pixel). The system must be able to render 640x200 pixels every 20 ms, with an overdraw factor of at least 2-3 (e.g., background, characters, and foreground - with the background pre-culled using BSP trees or portals to minimize overdraw). For the sake of simplicity, let us assume a processing rate of one pixel per clock cycle (with an overdraw factor of 2.2) and a color depth of Y7I5Q4 (where Y represents luminance, I represents an orange-axis chrominance component, and Q represents a purple-axis chrominance component). Visually, this format outperforms R5G6B5 while maintaining the same bit depth and scale linearity; to bridge the gap toward R8G8B8 quality, we can incorporate a programmable color filter at the video output stage. (Switching to a different memory configuration would allow for an increase in resolution, color depth, and the number of pixels processed per clock cycle.)

Since the color-difference components in a television signal are transmitted at a lower resolution, they can be blurred. To avoid the complexities of a 4:1:1 sampling structure, we can process the lower-order bits using a "diamond diffusion" pattern during rendering, and then pass the data through a filter when reading from video memory. In this scheme, every byte of the image data contains Y5I2Q1 components and is processed uniformly. The output filter uses a 2x2 window for the Y (luma) component and a 4x2 window for the color-difference components; while this may introduce slight banding, the result will be a standard television-style image.

We will employ a double-buffering strategy (displaying one buffer while filling the other). Since frames may be generated at either 50 Hz or 25 Hz depending on the task, we will allocate video memory for full-height frames - 640x400 pixels. Each frame occupies 256,000 bytes, requiring four 44256-type memory chips. This creates a 16-bit bus, where half the bandwidth is dedicated to reading (outputting to the television via the aforementioned filters) and the other half to writing (performed in blocks).

The processing of image blocks will take place within an ASIC (or FPGA). This block-level processing must handle not only color data but also depth (Z) values, a stencil buffer (for geometric shadows/rays using the Z-fail method), and a pixel validity bit (to eliminate the need to explicitly clear blocks).

Suppose that at a frequency of 50 Hz, a single block measures 48*56 pixels (containing data for only one television field - that is, with narrow pixels). This corresponds to 64 (16*4) blocks across the screen, with a 4-pixel overlap on each side. This overlap allows for the application of blur effects during the copy process to the video buffer - such as anti-aliasing, depth-of-field, bloom, or the masking of grid artifacts in rendered semi-transparent objects. This post-processing stage (which also encompasses fog, shadows, and light rays) utilizes data from the Z-buffer and stencil buffer. While the vertical overlap between blocks requires re-rendering, the horizontal overlap can be handled simply by re-indexing the X-coordinates in the buffer as the system iterates through the horizontal blocks. Consequently, the total area to be rendered is 640*56*4 = 143,360 pixels (12% greater than the theoretical minimum). At a refresh rate of 25 Hz, the screen would consist of 128 (16*8) blocks, each measuring 48*56 pixels, now with square pixels. A non-interlaced mode is also possible, allowing for a 640x200 image at 25 Hz with each pixel redrawn 4 times, or a 640x240

image with a redraw factor of 3.3. These redraw factors are
calculated based on the texture engine operating speed 14 MHz,
though other internal clock frequencies are possible within the
chip.

Lets calculate the required internal memory size. Assume color
is stored in an 8-bit format; the Z-buffer is logarithmic, with
a precision of 1 cm at a distance of 1 meter (8 bits are
sufficient); and the stencil buffer is 4-bit (allowing for up to
15 overlapping shadows, or 3 shadows and 3 light overlays at a
single point). Including a validity bit, this totals 48 56
(8 + 8 + 4 + 1) = 56,448 bits of memory. Even with
double-buffering (drawing to one buffer while copying another to
the video buffer), this would occupy less than half of an ASIC -
even one manufactured in a home laboratory using 1.2-micron
technology.

Texturing requires a higher data throughput than the pixel
stream sent to the display. Consequently, later generations of
gaming systems introduced packed textures. Consider a 4x4
block-based packing scheme, where each block occupies 32 bits.
Given the potential for hardware-accelerated noise generation
(such as Perlin noise - a feature not currently found in known
video systems), we can categorize textures into the following
types:

4-color textures (e.g., for environment mapping). These
textures are defined by 4 colors, one of which may be
transparent. In this format, 4x4 blocks store 2 bits per pixel.
Gradient-based textures with pixelated spots (e.g., skin). For
such a texture, a gradient axis and the color of the pixelated
spots are defined. Each 4x4 block is stored as a center color, a
gradient direction and intensity, and a pixel bitmask.
Arbitrary textures using two colors per 4x4 block. Each 4x4
block is stored as two colors and a pixel bitmask.

In realistic scenes, the average width of a triangle should be
4-8 pixels; otherwise, their flatness becomes apparent. By
maintaining multiple versions of textures at different scales,
we typically retrieve the same 4x4 blocks for adjacent pixels.
Furthermore, all the blocks accessed for a given triangle -
which are few in number - will almost always fit into an
internal buffer, with some blocks even being reused by the next
triangle in a sequence. Consequently, only a few texture memory
reads are required per triangle, even when bilinear filtering is
applied. This approach allows textures to be stored across four
44256 memory chips, providing 512 KB of capacity (supporting up
to 2048x1024 texels, excluding metadata, which can even fit
within the internal memory of an ASIC/FPGA).

Bump maps do not need to be stored explicitly; instead, they can
be generated on the fly using Perlin noise.

A separate set of four 44256 memory chips (512 KB) is used to
store geometry. We limit the scene to 65,536 polygons, which -
when combined with bump mapping - is sufficient even for scenes
on the scale of Shadow of the Colossus. Polygons are organized
into chains, and these chains are grouped into sub-objects that
share a common texture. Compact storage will be required: 32,768
vertices, each 6-8 bytes in size (containing, for example,
screen-space XY coordinates, 1/Z, UV coordinates - potentially
pre-divided by Z - and lighting or normal vector data), along
with 65,536 polygons organized into chains, with one new vertex
per polygon (2 bytes each). This amounts to approximately 384 KB
in total. Geometry data will need to be read much more
frequently than it is written, as the system must process 64
separate windows. To handle this, as data is received from the
processor, the system should simultaneously construct polygon
lists for each window in the form of linked chains (each entry
consisting of a 1-byte texture ID, a 1-byte polygon count, a
2-byte pointer to the start of the chain, and a 2-byte pointer
to the next element - requiring about 128 KB). Several geometry
storage strategies are possible: 1) a single instance, where
rendering pauses during updates (full memory capacity is only
available at a 25 Hz refresh rate); 2) a dual-instance approach,
where one instance is displayed while the other is being
generated (limiting capacity to 32,768 polygons); or 3) a
dual-instance approach that stores fewer polygons and performs
on-the-fly tessellation using XYZ and normal vector data.

Although this design calls for three DRAM blocks, the system can
be emulated on any FPGA development board equipped with SRAM.
Once debugged on an FPGA, a custom PCB with DRAM can be
fabricated (affordable desktop PCB milling machines are
available for home labs; at a 14 MHz clock frequency, one could
even wire the chips together on a breadboard). Following
experiments at 14 MHz using a television signal, the system
could be upgraded to 30 MHz with VGA output (incorporating SDRAM
chips), and so on.

A fully independent software ecosystem: In addition to the
aforementioned NedoPC, independent operating systems for various
types of computers have also been developed in Moscow (Phantom
OS [18], Kaspersky OS [19]), Saint Petersburg (iS-DOS [20],
Embox [21]), Novosibirsk (Excelsior [22]), Penza (QP OS [23]),
and other cities. In other words, this is a standard engineering
challenge that has been solved many times over in Russia.
Relying on foreign kernels is counterproductive to achieving
technological independence.
Production of peripherals: Keyboards are readily manufactured in Russia (for example, by the Ryazan-based company Master-Klyuch [24]). The Beshtau Group [25] also produces keyboards and mice. Dot-matrix printers (UD-M [26]) are likewise manufactured domestically. While there is no information regarding the production of scanners in Russia, similar optical sensors are used on satellites, and the mechanical components of scanners are quite simple (in fact, back in the 1990s, radio enthusiasts used to build scanners using dot-matrix printers [27]). A relatively simple USB 1.1 interface could be employed, though it would require setting up the production of the necessary connectors. In any case, if the need arises, all required peripherals can be manufactured within Russia.
Hard disk drive (HDD) production. Since the micromotors and read/write heads for modern HDDs can only be sourced from companies controlled by the U.S. or Japan, it would be more practical to shift focus toward solid-state storage - specifically SSDs and SD/MMC cards. It is worth noting that while domestically produced chips may not be able to compete with foreign counterparts in terms of capacity (currently limited to a maximum of 1 GB per chip) or price, having an independent source of non-volatile memory is crucial for data security.
Production of manufacturing equipment. At present, Russia has the capability to produce lasers, lithography systems, motors, and sensors - perhaps not the most high-precision versions, but sufficient for microchip fabrication. Plasma-processing and deposition systems are no more complex than the equipment already used in the field of nuclear physics. Chip-packaging equipment remains a challenge; however, overall, complete import substitution is achievable in the short term - with the notable exception of precision machinery for 3D chip assembly.
Production of consumables. While our information here is limited, Russia possesses the necessary raw materials, a world-renowned tradition in crystal growth, and existing production facilities for ultra-pure gases. It is also known that the company Mikron produces its own photoresist. This is a clear instance where technological independence also makes commercial sense.
Production of metrological equipment and standards. Unfortunately, there is no positive information to report regarding this area. In extreme cases, metrological equipment for a few strategic plants could be manufactured on an individual, custom basis by specialized research institutes. Once self-sufficiency is achieved, such equipment could also be sold commercially.

Conclusions

The data presented indicate that full technological independence in the field of computing is entirely achievable for Russia, though not through market-based methods.

This requires:

The creation of a unified design for a domestic computer (the architecture must be completely open to avoid "vendor lock-in" and patent trolling). To prevent corruption, the following conditions are also necessary:
1. No payments, prizes, or patent royalties for the adoption of the overall design or specific technical decisions.
2. The design must be comprehensible to a single specialist without the need to refer to external documents.
3. The design must be accompanied by a volume justifying the chosen technical solutions (a "rationale" or explanatory memorandum).
4. Technical experts must compare the various complete or partial proposals submitted and synthesize them into a single, unified design. This must be carried out by a small, specialized group possessing a comprehensive range of competencies: a processor designer, a video controller designer, an interface chip designer, a physical chip layout designer, a microchip manufacturing technologist, a machine-tool manufacturing technologist, a systems programmer, a compiler developer, and an applications programmer. No one else should participate in the meetings or the formulation of technical decisions, as sociology recognizes nine as the maximum number of members for an effective committee [28]. These specific experts would then lead the development of their respective components of the computer system, assuming responsibility for them under state funding, support, and oversight. (Beyond state-led initiatives, similar development efforts could also be undertaken by major corporate groups, such as AFK Sistema or Sber.)
Define a standard for a domestic operating system (OS) to serve as a foundation for application development. This standard must be entirely open, support real-time operation, and ensure trusted data processing. To prevent corruption, the following conditions must be met (in addition to those mentioned above): the standard must not be compatible with foreign operating systems - this avoids the emergence of "pseudo-domestic" products and prevents the recurrence of well-known flaws inherent in the POSIX standard [29]. (Should they wish, distributors of Linux-based systems can adapt to this domestic architecture on their own; they are, after all, competitors.)
Expand the field of topological optimization through the establishment of "Hacker Fab"-style laboratories. A large pool of such specialists will enable the maximum performance optimization of all computer hardware components.
Develop domestic DRAM using accessible manufacturing processes.
Develop domestic solid-state memory using accessible manufacturing processes.
Construct a production line for liquid-crystal or LED displays to replace the one that was shut down.
Compile an inventory of missing materials and components required for production equipment, and initiate their development in a laboratory setting.
Compile an inventory of missing metrological equipment and initiate its development in a laboratory setting.

A working group must be established to address these objectives.

List of Abbreviations

RAM (Random Access Memory) - includes SRAM (static RAM), DRAM (dynamic RAM), SDRAM (synchronous dynamic RAM), DDR, DDR2 - subsequent standards
OOP - Object-Oriented Programming
OS - Operating System
DBMS - Database Management System
ASIC - Application-Specific Integrated Circuit
FPGA - Field-Programmable Gate Array
RISC - Reduced Instruction Set Computer (architecture with a reduced, typically uniform, instruction set)

LITERATURE

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